PHYSICAL LAYER PRODUCT
PB-VSC8173-001
VSC8173
9.9-10.7Gb/s 16:1 Multiplexer with Clock Generator
F E A T U R E S :
Fully Compliant with OIF 99.102
SONET/SDH Jitter Compliant
622MHz Data Clock Input Modes
Superior Data Output Eyes
Low Power 1.7W (Typ)
+3.3V Single Supply
Continuous Tuning Operation from 9.953 to 10.709Gb/s Rates
155-168/622-670 MHz Reference Clock Input
Reliable 90-Ball BGA Package
Up to 85
C Case Temperature
A P P L I C A T I O N S :
SONET/SDH Networking
Transponder Modules
DWDM Systems
G.975/709 Forward Error Correction (FEC)
Gigabit Ethernet
Telecommunications Transmission Systems
Test Equipment
B E N E F I T S :
Provides Lowest Power Solution in its Performance Class
Integrated PLL Based Clock Generator
Meets SONET/SDH Jitter Generation Requirements
OIF 99.102 Compliant LVDS Interface
Thermal Expansion of TBGA Package is Matched to the PC
Board for High Reliability
Input FIFO to Simplify Parallel Interface Timing
Loss-of-Lock and Internal Temperature Sensing to Assist in
Monitoring Device Operation
Data Polarity Invert and Bit Order Swap for Ease of Layout
PHYSICAL LAYER PRODUCTS
741 Calle Plano
Camarillo, CA 93012
Tel: 805.388.3700
Fax: 805.388.7565
www.vitesse.com
Your Partner for Success.
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or sales@vitesse.com
VSC8173
2002 Vitesse Semiconductor Corporation
9.9-10.7Gb/s 16:1 Multiplexer with Clock Generator
S P E C I F I C A T I O N S :
9.953 to 10.709Gb/s Continuous Operation
Data Output Voltage Swing: 600 mV (Min)
Data Output Rise/Fall: 25ps (Typ)
10ps Wideband Jitter (Max)
Supply Voltage: 3.3V (Typ)
Total Power Dissipation: 1.7W (Typ)
Operating Temperature Range: 0
C to +85C (case)
15x15mm Low Profile 90 Ball TBGA (Taped BGA) Package
The VSC8173 consists of a 16:1 multiplexer and a clock generator
for use in SONET STS-192/SDH STM-64 systems. The 16:1
multiplexer accepts 16 parallel LVDS inputs at a data rate of
622.08Mb/s to 669.31Mb/s. This parallel data stream is then
serialized into a 9.953Gb/s to 10.709Gb/s output. 622MHz data
clock input mode is supported. The clock generator creates the 9.953GHz to 10.709GHz
clock signal used to re-time the transmitted serialized data. The clock generator
requires a 155 to 168MHz or 622 to 670MHz LVPECL reference clock input. To ease
timing constraints on the parallel interface, a 16-bit wide FIFO is included. A divided-by-
16 or divide-by-64 LVDS clock output is available for use as a clock input to the parallel
data source. Additional features include Bit Order Swap and Data Polarity Invert. To
assist in monitoring device operation a Loss-of-Lock alarm and internal temperature
sensing are provided. The device is packaged in a modified 90-Ball Grid Array (BGA).
V S C 8 3 7 3 B L O C K D I A G R A M :
G E N E R A L D E S C R I P T I O N :
REFOUT+
REFOUT-
RESETN
OVERFLOW
BITORDER
AUTORSTN
DINVERT
REFSEL
CKMODE
2
DSKEW[0:1]
LOLN
NOREFN
DETECT
LOCK
LOSS
OF
DOUT+
DOUT-
D15-
D15+
D1+
D0-
D0+
D14+
D14-
DCK+
DCK-
16:1
TIMING
REFCK+
REFCK-
PLL
FIFO
7-BIT
9.9-10.7G
RST
OVR
D1-
DELAY
GENERATOR
DELAY
DIV
CK/32
CK/16
CK16_64+
CK16_64-
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