Rev. 1.6.3 - 9/29/04 VITESSE - CONFIDENTIAL & PROPRIETARY - DO NOT COPY WITHOUT PERMISSION - Page 1 of 21 -
SimpliPHY
VSC8201
PCB Design and Layout Guide
Single Port 10/100/1000BASE-T
and 1000BASE-X
PHY
Introduction
This purpose of this application note in conjunction with the VSC8201 Datasheet is to provide information to assist in the design and lay-
out of the VSC8201 Gigabit Ethernet Transceiver.
Power Supply Organization and Decoupling
The VSC8201 requires a 3.3v and a 1.5v power supply source for operation using GMII, MII or TBI MAC interfaces. In RGMII and RTBI
modes, an additional 2.5v supply is needed as specified by the RGMI/RTBI standard. The VSC8201 can be powered using the following
options:
2 separate supplies, 3.3v and 1.5v respectively.
A single 3.3v supply. This is done by using the optional on-chip regulator control circuit, which drives a simple external series pass
type supply regulator (MOSFET) to generate the 1.5v core power supply.
PCB Power Plane Organization
It is recommended that the PCB power plane(s) in a system be divided into four separate regions:
Power Supply Filtering and Decoupling
For best performance, each power supply region should contain capacitors for both bulk decoupling and for local high-frequency decou-
pling. This is summarized in the following tables:
Table 1: Power Supply Plane Regions
PCB Power
Plane
Description
Nominal
Supply Voltage
Current
a
a. Test conditions: Room temperature (25
o
C), 1000BASE-T data, full duplex, minimum IPG, 64-byte packets, RGMII MAC active, excluding
regulator power dissipation but including external twisted pair termination; all worst case current figures have all nominal power supplies
scaled by +5%.
LQFP Supply Names
b
b. Refer VSC8201 Datasheet to correlate supply names with part pin numbers.
Typ
Max
V+IO
Digital Input/Output
buffer supply
3.3v/2.5v
8mA
11mA
VDDIO
V+A33
Filtered analog 3.3v
supply
3.3v
101mA
111mA
TXVDD, VDDREC33,
VDDPLL33
V+A15
Filtered analog 1.5v
supply
1.5v
41mA
48mA
VDDREC15, VDDPLL15
V+DIG
Digital core supply
1.5v
350mA
423mA
VDDDIG
VSC8201DL
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The following figure shows the proposed layout for the local decoupling capacitors. The figure is approximately drawn to scale for stan-
dard 0603 size capacitors. Vias to the power and ground planes immediately in the vicinity of the capacitors provide a low inductive path
and aid in heat dissipation.
Table 2: Power Supply Decoupling for separate 3.3v and 1.5v Power Supplies
PCB Power Plane
Bulk Decoupling required
Local Decoupling Required
V+IO
1 pair of 22uF, 1uF
Four 0.1uF capacitors
V+A33
1 pair of 22uF, 1uF and 1 10uF
Two 0.1 uF capacitors
V+A15
1 pair of 2.2uF, 1uF
One 0.1 uF capacitor
V+DIG
1 pair of 22uF, 1uF
Four 0.1uF capacitors
Table 3: Power Supply Decoupling for single 3.3v Supply and Optional fixed 1.5v Regulator
PCB Power Plane
Bulk Decoupling required
Local Decoupling Required
V+IO
1 pair of 22uF, 1uF
Four 0.1uF capacitors
V+A33
1 pair of 22uF, 1uF and 1 10 uF
Two 0.1uF capacitors
V+A15
1 pair of 2.2uF, 1uF
One 0.1 uF capacitor
V+DIG
2.2uF
Four 0.1uF capacitors
VSC8201
128 LQFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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21
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27
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38
10
2
10
1
10
0
99
98
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39
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122
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125
126
127
128
Note:Place vias close to or under neath the capacitor pads for
low inductive path and higher heat dissipation rate.
0.1 uF
Figure 1: Local High-Frequency decoupling Capacitor Layout - LQFP package
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In addition, a ferrite bead should be used to isolate each analog supply from the rest of the board. The bead should be placed in series
between the bulk decoupling capacitors and the local decoupling capacitors.
Figure 3: Power Supply Decoupling Schematic
The beads should be chosen to have the following characteristics:
Current Rating of at least 150% of the maximum current of the power supply.
Impedance of 80 to 100W at 100Mhz.
Recommended beads are:
Panasonic EXCELSA39 or similar.
Steward HI 1206N101R-00 or similar.
Note:Place vias close to or under neath the capacitor pads for
low inductive path and higher heat dissipation rate.
0.1 uF
.
A
B
C
1
2
3
4
56
78
9
1
0
F
K
J
H
G
E
D
Figure 2: Local High-Frequency decoupling Capacitor Layout - LBGA package
VSC8201DL
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Since all PCB designs yield unique noise coupling behavior, not all ferrite beads or decoupling capacitors may be needed for every
design. For this reason, it is recommended that system designers provide and option to replace the ferrite beads with zero-ohm resistors,
once thorough evaluation of system performance is completed.
PCB Chassis ground Region
To isolate the board from the ESD events and to provide a common-mode noise ground path, a separate chassis ground region should
be allocated. This should provide an electrical connection to the external chassis and the shield ground to discharge common-mode
noise through a 75-ohm resistor and a single 1000pF 2kV capacitor. See "VSC8201 System Schematic" in the datasheet.
Figure 4: Ground Plane Layout
Key points
The chassis ground and the PCB ground should have as much separation as possible. 45 mils or greater is recommended.
There should be no power or ground plane beneath the primary and secondary coils of the transformer.
VSC8201DL
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Regulator Circuit
For systems with a single power supply, the VSC8201 provides an option to generate the 1.5v supply from the 3.3v supply by using the
on chip regulator. The internal regulator is enabled by having a 10k pull-up on the REG_EN pin.
To use the Regulator the following additional components are required:
FET device, similar to Fairchild FDT439N.
For decoupling, two 0.0047uF capacitors with 10% tolerance or better. NPO, X7R or X5R are all acceptable.
Systems with single 3.3v,+/-10% Wake on LAN supply
The following figure shows the circuit for generating the 1.5v supply using a 3.3v,+/-10% supply
Figure 5: Regulator Circuit using 3.3v, +/-10% supply
Key points
Place a 0.0047uF capacitor as close to REG_OUT as possible.
Place a 0.0047uF capacitor as close to the FET as possible.
Tie the GND line together with VREFN, capacitor connected to REF_FILT, resistor R4 (See figure above) and then connect to a com-
mon ground.
VREFP should be connected to the analog 3.3v plane i.e. V+A33.
Using ActiPHY
TM
Power Management
The VSC8201 supports a new power saving mode called ActiPHY
TM
, particularly suited to power saving applications like laptop comput-
ers with wake on LAN capability.
1
When in ActiPHY
TM
mode the PHY is in one of two power down states and has the ability to detect valid signal energy levels at the
media pins and convey it to the station manager.
1. Refer VSC8201 Datasheet.
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