VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
G52247-0, Rev 4.2
Page 1
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
General Description
The VSC834 is a monolithic 17x17 asynchronous crosspoint switch designed to carry broadband data
streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor inter-
face that allows random access programming of each output port. A high degree of signal integrity is main-
tained through the chip through fully differential signal paths.
The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 17:1
multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be pro-
grammed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The
signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input.
Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An inter-
rupt pin is provided to signal LOA, after which an external controller can query the chip to determine the chan-
nel(s) on which the fault occurred.
Each output driver is a fully differential switched current driver with on-die back-terminations for maxi-
mum signal integrity. Data inputs are terminated on die through 50
resistors connected to V
TERM
.
The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with
a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and
programming. Program buffering is provided to allow multiple program assignments to be queued and issued
simultaneously via a single configure command.
VSC834 Block Diagram
17 Input by 17 Output Crosspoint Switch
2.5Gb/s NRZ Data Bandwidth
42 Gb/s Aggregate Bandwidth
TTL Compatible
P Interface
Differential PECL Data Inputs
On-chip 50
Input Terminations
50
Source Terminated PECL Output Drivers
Single 3.3V Supply
9W Maximum Power Dissipation
High Performance 256 Pin BGA Package
A0
A16
P Interface
Y0
Y16
Control Logic
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
Page 2
G52247-0, Rev 4.2
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 1: Detailed Block Diagram:
Functional Description
Data Paths
All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a
nominal impedance of 50
. All input termination resistors are tied to V
TERM
.
Data outputs are provided through differential current switches with on-chip terminations that produce a
PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels
when terminated in 50
to 2.0V. Other termination voltages are possible, such as to V
CC
or 1.3V, but the volt-
age level of the output swing will be shifted from its nominal value. The common-mode voltage of the output
swing can be adjusted using the VCOM pin. The adjustment range is not calibrated, but typically allows for
about +200mV of adjustment in the output common-mode voltage.
Output channels can be powered off in pairs if fewer than 17 outputs are required. By connecting the VEE
pin associated with a given pair of outputs to V
CC
, the output pairs will pull to V
CC
and chip power will be
reduced by roughly 200mW.
17x17
Switch Core
A, AN[16:0]
Y, YN[16:0]
LO
A
Monitor
Program Memory
17
Control Interface
DATA[4:0], ADDR[5:0]
ALE, CSB, WRB, RDB INTB,
MONCLK, CONFIG
Output Dr
iv
ers
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
G52247-0, Rev 4.2
Page 3
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Programming Interface
The switch core is programmed through a parallel interface circuit that allows random reads or writes to the
program memory array. The program memory array is buffered to allow multiple programming instructions to
be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate.
The program data is composed of two parts: output address and input address. The output address, denoted
by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[4:0],
specifies which input port the switch slice should connect to. The format of the program data is simple binary,
where the binary value maps directly to the switch slice position and/or input port number. For example:
ADDR[5:0] (000100) / DATA[4:0] (00110) would direct output channel Y4 to connect to input channel A6. The
programming state may be verified (read back) by applying the address of the desired output and asserting
RDB. The programming state is unknown at power-on. Additional address space is provided for access to the
monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL
(see Table 6).
Table 1: Signal Table
Loss of Activity (LOA) Monitoring
The LOA function consists of an activity monitor on each input channel, connected directly to the pads.
The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying
the address (See Table 2) of the monitor register corresponding to the signal of interest and asserting RDB. Each
monitor register is four bits in length, covering the state of four inputs or outputs. There is one extra one-bit
monitor for each of the 17
th
input and 17
th
output. The state of each monitor is transferred to the register period-
ically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected.
Pin
I/O
Description
D[5:0]
B
Bidirectional data bus to transfer data to/from internal program registers
A[5:0]
I
Address bus to select internal program registers for read-write operations
ALE
I
Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally
when low.
CSB
I
Chip Select (Active Low): assert this pin whenever the part is being read or programmed.
WRB
I
Write (Active Low): program data will be transferred to the first level internal registers on the rising
edge of this signal (when CSB is also low).
RDB
I
Read (Active Low): program data from the internal program or monitor registers will be read out on the
data bus when this signal goes low (with CSB also low).
INTB
O
Interrupt (Active Low): this signal is asserted when an LOA condition is found
CONFIG
I
Configure (Active High): assert this signal to transfer queued program information from the first-level
internal registers to the second-level registers, making the programming take effect. This signal may be
tied high to leave the second-level registers transparent so all programming will take effect
immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a high-
order bit of the address bus
MONCLK
I
Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not
expected to exceed 3MHz.
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
Page 4
G52247-0, Rev 4.2
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by
asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt
will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If
multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been
read.
The LOA circuitry requires a minimum signal level of 30-150 mV peak-peak to recognize an input as
active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination
voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal
level can be adjusted with the VHYS pin, which can set the threshold from zero to the maximum allowed input
swing. The VHYS pin will self-bias to a nomial value that will be appropriate for most applications (30-150mV
p-p input level). Although uncalibrated for nominal level, gain and linearity, the VHYS pin can be externally
set to adjust the threshold level over the entire range of the input signal, from zero to the maximum level
allowed at the input.
Table 2: Memory Map
Address
Access
Description
00h
R/W
Output Y0's programmed input channel ( write and then assert CONFIG to program)
01h
R/W
Output Y1's programmed input channel
...
...
...
10h
R/W
Output Y16's programmed input channel
11h
R/W
Internal output Y17's programmed input channel
...
...
...
20h
R/W
Internal output Y32's programmed input channel
21h
R/O
Rx Activity monitor for inputs A0, A1,A2,A3 ( Logic `1'=No activity)
22h
R/O
Rx Activity monitor for inputs A4, A5,A6,A7
23h
R/O
Rx Activity monitor for inputs A8, A9,A10,A11
24h
R/O
Rx Activity monitor for inputs A12, A13,A14,A15
25h
R/O
Rx Activity monitor for input A16
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
G52247-0, Rev 4.2
Page 5
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Table 3: Data Path
Note: Unless otherwise stated, all specifications are guaranteed but not tested.
Note 1: Skew between any two input channels to a given output.
Note 2: Skew between any two output channels from the same input channel.
Note 3: Required for high-speed output rise/fall spec at F
RATE
=2.5 Gbits/s. For lower rate signals, use 0.375/F
RATE
Note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data
Figure 2: Interrupt Timing (Change in Monitor State Registers)
Figure 3: Interrupt Timing (No Change in Monitor State Registers)
Parameter
Description
Min
Typ
Max
Units
F
RATE
Data rate
-
-
2.5
Gb/s
T
ISKW
Input channel delay skew (1)
-
300
-
ps
T
OSKW
Output channel delay skew (2)
-
300
-
ps
t
R
, t
F
High-speed input rise/fall times, 20% to 80% (3)
-
-
150
ps
t
R
, t
F
High-speed output rise/fall times, 20% to 80%
-
-
150
ps
t
jP
Output data eye jitter, peak-peak, 2
23
PRBS (4)
-
-
100
ps
MONCLK
Monitor State
Monitor State Reg
INTB
CSB
RDB
ADDR[5:0]
DATA[4:0]
T
sRDB
T
hRDB
T
tsDATA
MONCLK
Monitor State
Monitor State Reg
INTB
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