Document : 1G5-0155 Rev.1
Page 1
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank,
8,388,608 - word x 8 - bit x 4 - bank, or 4,194,304 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
Single 3.3V (
) power supply
High speed clock cycle time : 7.5ns/10ns
Fully synchronous with all signals referenced to a positive clock edge
Programmable CAS Iatency (2,3)
Programmable burst length (1,2,4,8,& Full page)
Programmable wrap sequence (Sequential/Interleave)
Automatic precharge and controlled precharge
Auto refresh and self refresh modes
Quad Internal banks controlled by A13 & A14 (Bank select)
Each Banks can operate simultaneously and independently
I/O level : LVTTL compatible
Random column access in every cycle
x4, x8, x16 organization
Input/Output controlled by DQM, LDQM, UDQM
8,192 refresh cycles/64ms
Burst termination by burst stop and precharge command
Burst read/single write option
The information shown is subject to change without notice.
0.3V
Document : 1G5-0155 Rev.1
Page 2
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
Pin Description
VG36256401/VG36256801/VG36256161
Pin Name
Function
Pin Name
Function
A0 - A12
A13, A14
Address inputs
Bank select
DQM,
LDQM,
UDQM,
Upper DQ Mask enable,
Lower DQ Mask enable
DQ0 ~ DQ15
Data - in/data - out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
CS
Chip select
WE
Write enable
V
DDQ
Supply voltage for DQ
V
SS
Ground
V
SSQ
Ground for DQ
V
DD
Power (+ 3.3V)
P
in Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
44
43
42
23
24
25
26
27
29
28
31
30
36
35
34
33
32
38
37
39
40
41
46
45
47
48
49
50
51
52
53
54
15
VG36256401 X 4
V
DD
NC
V
DDQ
V
SSQ
DQ0
V
DDQ
CAS
RAS
WE
A
10
/AP
A14/(BA0)
V
DD
NC
NC
V
SSQ
CS
NC
NC
DQ1
NC
VG36256801 X 8
VG36256161 X 16
V
DD
NC
A
0
A13/(BA1)
A
1
A
2
A
3
A14/(BA0)
A13/(BA1)
V
DD
DQ0
V
DDQ
V
SSQ
DQ2
V
DDQ
CAS
RAS
WE
A
10
/AP
A14/(BA0)
V
DD
DQ1
DQ3
V
SSQ
CS
DQ4
DQ5
DQ6
DQ7
V
DD
LDQM
A
0
A13/(BA1)
A
1
A
2
A
3
V
DD
DQ0
V
DDQ
V
SSQ
DQ1
V
DDQ
CAS
RAS
WE
A
10
/AP
V
DD
NC
NC
V
SSQ
CS
DQ2
NC
DQ3
NC
V
DD
NC
A
0
A
1
A
2
A
3
V
SS
NC
V
SSQ
V
DDQ
DQ3
V
SSQ
CLK
CKE
DQM
A
8
A
11
V
SS
NC
NC
V
DDQ
NC
NC
DQ2
NC
V
SS
NC,VREF
A
7
A
9
A
6
A
5
A
4
V
SS
DQ7
V
SSQ
V
DDQ
DQ6
V
SSQ
CLK
CKE
DQM
NC
NC
V
DDQ
DQ5
NC
DQ4
NC
V
SS
NC,VREF
V
SS
DQ15
V
SSQ
V
DDQ
DQ13
V
SSQ
CLK
CKE
UDQM
DQ14
DQ12
V
DDQ
DQ11
DQ10
DQ9
DQ8
V
SS
NC,VREF
A
12
A
8
A
11
V
SS
A
7
A
9
A
6
A
5
A
4
A
12
A
8
A
11
V
SS
A
7
A
9
A
6
A
5
A
4
A
12
Document : 1G5-0155 Rev.1
Page 3
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
Block Diagram
CLK
CKE
Clock
Generator
CS
RAS
Mode
Register
Column
Address
Buffer
&
Burst
Counter
CAS
WE
C
o
m
m
a
n
d
D
e
c
o
d
e
r
C
o
n
t
r
o
l
L
o
g
i
c
Address
Row
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
R
o
w
D
e
c
o
d
e
r
Data Control Circuit
DQ
DQM
L
a
t
c
h
C
i
r
c
u
i
t
I
n
p
u
t
&
O
u
t
p
u
t
B
u
f
f
e
r
(Bank C)
(Bank D)
Document : 1G5-0155 Rev.1
Page 4
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
V
DD
, V
DDQ
-0.5 to + 4.6
V
Short circuit output current
I
OUT
50
mA
Power dissipation
P
D
1.0
W
Operating temperature
T
OPT
0 to + 70
J
Storage temperature
T
STG
-55 to + 125
J
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage
V
IH
2.0
V
DD
+ 0.3
V
1
Input Low Voltage
V
IL
-0.3
0.8
V
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
DD,
V
DDQ
3.0
3.3
3.6
V
Input High Voltage, all inputs
V
IH
2.0
V
DD
+ 0.3
V
Input Low Voltage, all inputs
V
IL
-0.3
0.8
V
Capacitance
(Ta=25C, f = 1MHZ)
Notes : 1. Capacitance measured with effective capacitance measuring method.
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance (CLK)
C
11
2.5
4
pF
1
Input capacitance (all input pins except data
pins.)
C
12
2.5
5
pF
1
Data input/output capacitance
C
I/O
4.0
6.5
pF
1
Note: 1. Overshoot limit: V
IH
(max)=V
DDQ
+2.0V with a pulse with
2. Urdershoot
limit: V
IL
(min)=V
SSQ
-2.0V with a pulse with
and -1.5v with a pulse
3ns
<
3ns
<
5ns
<
Document : 1G5-0155 Rev.1
Page 5
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Notes : 1. I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
2. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3. I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
4. For LVTTL compatible.
Parameter
Symbol
Test Conditions
-75
-8H
Unit
Notes
Min
Max
Min
Max
Operating current
I
CC1
Burst length = 1
One bank active
t
RC
t
RC(MIN.)
, Io = 0mA
x4
145
115
mA
1
x 8
155
125
x16
165
135
Precharge standby
current in Power
down mode
I
CC2P
CKE
V
IL(MAX.)
t
CK
= min.
2
2
mA
I
CC2PS
CKE
V
IL(MAX.)
t
CK
=
2
2
Precharge standby
current in Nonpower
down mode
I
CC2N
CKE
V
IH(MIN.)
t
CK
= min.
CS
V
IH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
20
20
mA
I
CC2NS
CKE
V
IH(MIN.)
t
CK
=
CLK
V
IL(MAX.)
Input signals are stable.
7
7
Active standby current
in Power
down mode
I
CC3P
CKE
V
IL(MAX.)
t
CK
= min.
7
7
mA
I
CC3PS
CKE
V
IL(MAX.)
t
CK
=
5
5
Active standby
current in Nonpower
down mode
I
CC3N
CKE
V
IH(MIN.)
t
CK
= min.
CS
V
IH(MIN.)
Input signals are changed one
time during 2CLKs
30
30
mA
I
CC3NS
CKE
V
IH(MIN.)
t
CK
=
CLK
V
IL(MAX.)
Input signals are stable.
20
20
Operating current
(Burst mode)
I
CC4
t
CK
t
CK(MIN.
Io = 0mA
All banks Active
x4
150
120
x 8
160
130
mA
2
x16
170
140
Refresh current
I
CC5
t
RC
= 4 x t
RC(MIN)
190
190
mA
3
Self refresh Current
I
CC6
CKE
0.2V
1
1
mA
Input Ieakage current
(Inputs)
l
LI
V
IN
0, V
IN
V
DD(MAX)
Pins not under test = 0V
-1
1
-1
1
uA
Intput leakage current
(I/O pins)
l
LO
V
OUT
0, V
OUT
V
DD(MAX)
DQ# in H - Z., Dout Disabled
-1.5
1.5
-1.5
1.5
uA
Output Low Voltage
V
OL
I
OL
= 2mA
0.4
0.4
V
4
Output High Voltage
V
OH
I
OH
= -2mA
2.4
2.4
V
4
PDF 
ZIP