Document : 1G5-0127
Rev2
Page 1
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 1,048,576 - word x 16-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
Single 3.3V (
) power supply
High speed clock cycle time : 8/10ns
Fully synchronous with all signals referenced to a positive clock edge
Programmable CAS Iatency (2,3)
Programmable burst length (1,2,4,8,&Full page)
Programmable wrap sequence (Sequential/Interleave)
Automatic precharge and controlled precharge
Auto refresh and self refresh modes
Quad Internal banks controlled by A12 & A13 (Bank select)
Each Bank can operate simultaneously and independently
LVTTL compatible I/O interface
Random column access in every cycle
X16 organization
Input/Output controlled by LDQM and UDQM
4,096 refresh cycles/64ms
Burst termination by burst stop and precharge command
Burst read/single write option
The information shown is subject to change without notice.
0.3V
Document : 1G5-0127
Rev2
Page 2
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Pin Configuration
Pin Description
VG36641641
Pin Name
Function
Pin Name
Function
A0 - A11
A12,A13
Address inputs
Bank select
LDQM
UDQM
Upper DQ Mask enable,
Lower DQ Mask enable.
DQ0 ~ DQ15
Data - in/data - out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
CS
Chip select
WE
Write enable
V
DDQ
Supply voltage for DQ
V
SS
Ground
V
SSQ
Ground for DQ
V
DD
Power ( + 3.3V)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
44
43
42
VG36641641 (2)
V
DD
DQ0
V
DDQ
V
SSQ
DQ4
V
DDQ
CAS
RAS
WE
A
10
A13/BA0
A
1
A
2
A
3
V
DD
V
SS
DQ15
V
SSQ
DQ13
V
DDQ
DQ11
V
SS
DQ9
V
DDQ
NC
CLK
UDQM
CKE
NC
V
SS
A
9
A
8
A
7
A
6
A
5
A
11
DQ10
23
24
25
26
27
29
28
31
30
36
35
34
33
32
38
37
39
40
41
46
45
47
48
49
50
51
52
53
54
15
DQ2
DQ6
V
SSQ
V
DD
LDQM
CS
A12/BA1
A
0
A
4
DQ8
DQ12
DQ14
V
SSQ
DQ1
DQ3
DQ5
DQ7
Document : 1G5-0127
Rev2
Page 3
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Block Diagram
CLK
CKE
Clock
Generator
CS
RAS
Mode
Register
Column
Address
Buffer
&
Burst
Counter
CAS
WE
C
o
m
m
a
n
d
D
e
c
o
d
e
r
C
o
n
t
r
o
l
L
o
g
i
c
Address
Row
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
R
o
w
D
e
c
o
d
e
r
Data Control Circuit
DQ
DQM
L
a
t
c
h
C
i
r
c
u
i
t
I
n
p
u
t
&
O
u
t
p
u
t
B
u
f
f
e
r
Bank C
Bank D
Document : 1G5-0127
Rev2
Page 4
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
peumanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
V
DD
, V
DDQ
-0.5 to + 4.6
V
Short circuit output current
I
OUT
50
mA
Power dissipation
P
D
1.0
W
Operating temperature
T
OPT
0 to + 70
C
Storage temperature
T
STG
-55 to + 125
C
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage
V
IH
2.0
V
DDQ
+ 2.0
V
2
Input Low Voltage
V
IL
V
SSQ
-2.0
0.8
V
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
DD,
V
DDQ
3.0
3.3
3.6
V
Input High Voltage, all inputs
V
IH
2.0
-
V
DD
+ 0.3
V
Input Low Voltage, all inputs
V
IL
-0.3
-
0.8
V
Capacitance
(Ta = 25C, f = 1MHZ)
Notes : 1. Capacitance measured with effective capacitance measuring method.
2. The overshoot and undershoot voltage duration is
3ns with no input clamp diodes.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input capacitance (All input pins except CLK pin)
C
in
2.5
3.75
5.0
pF
1
CLK pin
C
CLK
2.5
3.25
4.0
pF
1
Data input/output capacitance
C
I/O
4.0
5.25
6.5
pF
1
Document : 1G5-0127
Rev2
Page 5
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Notes:
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
VG36641641B
-7
-8
Unit
Notes
Min
Max
Min
Max
Operating current
I
CC1
Burst length = 1
One bank active
t
RC
t
RC(MIN.)
, Io = 0mA
CL = 3
130
130
mA
1
CL = 2
130
130
Precharge standby
current in power
down mode
I
CC
2P
CKE V
IH(MAX.)
t
CK
= 10ns
2
2
mA
I
CC
2PS CKE V
IH(MAX.)
t
CK
=
2
2
Precharge standby current
in Nonpower down mode
I
CC
2N
CKE V
IH(MIN.)
t
CK
= 10ns.
CS V
IH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
25
25
mA
I
CC
2NS CKE V
IH(MIN.)
, tCK =
CLK V
IL(MAX.)
Input signals are stable.
7
7
Active standby current in
power down mode
I
CC
3P
CKE V
IL(MAX.)
, t
CK
= 10ns
7
7
mA
I
CC
3PS CKE V
IL(MAX.)
, t
CK
=
5
5
Active standby current in
Nonpower down mode
I
CC
3N
CKE V
IH(MAX.)
, t
CK
= 10ns
CS V
IH(MIN.)
Input signals are changed
one time during 2CLKs.
40
40
mA
I
CC
3NS CKE V
IH(MIN.)
t
CK
=
CLE
V
IL
(MAX.)
Input signals are stable.
20
20
Operating current
(Burst mode)
I
CC4
t
CK
t
CK(MIN.)
, Io = 0mA
All banks Active
CL = 3
170
170
mA
2
CL = 2
135
120
Refresh current
I
CC5
t
RC
t
RC(MIN.)
220
200
mA
3
Self refresh current
I
CC6
CKE 0.2V
1
1
mA
Input leakage current
I
LI
V
IN
0, V
IN
V
DD
+ 0.3V
Pins not under test = 0V
- 5
5
-5
5
Output leakage current
I
LO
V
OUT
0, V
OUT
V
DD
(MAX)
DQ# in H - Z., Dout disabled
- 5
5
-5
5
Output Low Voltage
V
OL
I
OL
= 2mA
0.4
0.4
mA
4
Output High Voltage
V
OH
I
OH
= -2mA
2.4
2.4
mA
4
CKE
V
CKE
V
CKE
V
CKE
V
CKE
V
CKE
V
CKE
V
CKE
V
A
CKE
V
A
1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC1 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC4 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
3. ICC5 is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
4. For LVTTL compatible, VG36648041.
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