Document:1G5-0145
Rev.1
Page 1
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Overview
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
Fast access time from clock: 4.5/5/5.5ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single + 3.3V power supply
Input Reference Voltage : Vref = 1.5V 0.2V
Interface: LVTTL and SSTL_3
JEDEC 100-pin Plastic QFP package
0.3V
Document:1G5-0145
Rev.1
Page 2
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Key Specifications
VG4616321/VG4616322
-5/6/7
t
CK
Clock Cycle time(min.)
5/6/7 ns
t
RAS
Row Active time(min.)
30/36/40 ns
t
AC
Access time from CLK(max.)
4.5/5/5.5 ns
t
RC
Row Cycle time(min.)
45/54/62 ns
DQ3
1
V
DDQ
2
DQ4
3
DQ5
4
V
SSQ
5
DQ6
6
DQ7
7
V
DDQ
8
DQ16
9
DQ17
10
11
DQ18
12
DQ19
13
V
DDQ
14
15
16
17
DQ21
18
19
V
SSQ
20
DQ23
21
22
DQM0
23
24
WE
25
CAS
26
RAS
27
CS
28
BS
29
A8
30
DQ28
V
DDQ
DQ27
DQ26
V
SSQ
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
DQ11
DQ10
DQ9
DQ8
NC/Vref
DQM3
DQM1
CLK
CKE
DSF
NC
A9
V
SSQ
V
DD
V
SS
DQ20
DQ22
V
DDQ
DQM2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ24
V
DD
V
SSQ
V
DDQ
D
Q
2
9
V
S
S
Q
D
Q
3
0
D
Q
3
1
V
S
S
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
D
Q
0
D
Q
1
D
Q
2
N
C
V
D
D
V
S
S
Q
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
8
1
A
7
A
6
A
5
A
4
V
S
S
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
A
3
A
2
A
0
N
C
V
D
D
A
1
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
5
0
Document:1G5-0145
Rev.1
Page 3
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
CS
RAS
CAS
WE
DSF
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
ADDRESS
BUFFER
REFRESH
COUNTER
MODE
REGISTER
SPECIAL
MODE
REGISTER
CONTROL
SIGNAL
GENERATOR
COLOR
REGISTER
MASK
REGISTER
Column Decoder
1024 X 256 X 32
CELL ARRAY
(BANK #0)
R
o
w
D
e
c
o
d
e
r
Sense Amplifier
Sense Amplifier
1024 X 256 X 32
CELL ARRAY
(BANK #1)
R
o
w
D
e
c
o
d
e
r
Column Decoder
DQs
BUFFER
CLK
CKE
DQM0~3
DQ0
DQ31
|
A0
A8
~
BS
A9
Block Diagram
Document:1G5-0145
Rev.1
Page 4
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Table 1 shows the details for pin number, symbol, type, and description.
Table 1. Pin Description of VG4616321
Pin Num-
ber
Symbol Type Description
55
CLK
Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and con-
trol the output registers.
54
CKE
Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When both banks are in
the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during Power Down
and Self Refresh modes providing low standby power.
29
BS
Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or Bank-
Precharge command is being applied. BS is also used to program the 10th bit of
the Mode and Special Mode registers.
30-34,
47-51
A0-A9
Input Address Inputs: A0-A9 are sampled during the BankActivate command (row
address A0-A9) and Read/Write command (column address A0-A7 with A9 defin-
ing Auto Precharge) to select one location out of the 256K available in the respec-
tive bank. During a Precharge command, A9 is sampled to determine if both banks
are to be precharged (A9 = HIGH). The address inputs also provide the op-code
during a Mode Register Set or Special Mode Register Set command.
28
CS
Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the com-
mand decoder. All commands are masked when CS is sampled HIGH. CS provides
for external bank selection on systems with multiple banks. It is considered part of
the command code.
27
RAS
Input Row Address Strobe: The RAS signal defines the operation commands in con-
junction with the CAS and WE signals, and is latched at the positive edges of CLK.
When RAS and CS are asserted "LOW" and CAS is asserted "HIGH", either the
BankActivate command or the Precharge command is selected by the WE signal.
When the WE is asserted "HIGH" the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the WE is asserted
"LOW", the Precharge command is selected and the bank designated by BS is
switched to the idle state after precharge operation.
26
CAS
Input Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals, and it is latched at the positive edges of
CLK. When RAS is held "HIGH" and CS is asserted "LOW", the column access is
started by asserting CAS "LOW". Then, the Read or Write command is selected by
asserting WE "LOW" or "HIGH".
25
WE
Input Write Enable: The WE signal defines the operation commands in conjunction with
the RAS and CAS signals, and it is latched at the positive edges of CLK. The WE
input is used to select the BankActivate or Precharge command and Read or Write
command.
53
DSF
Input Define Special Function: The DSF signal defines the operation commands in
conjunction with the RAS and CAS and WE signals, and it is latched at the positive
edges of CLK. The DSF input is used to select the masked write disable/enable
command and block write command, and the Special Mode Register Set cycle.
Document:1G5-0145
Rev.1
Page 5
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
23,56,24,
57
DQM0-
DQM3
Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.
Input data is masked when DQM is sampled HIGH during a write cycle. Output data
is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.
DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8,
and DQM0 masks DQ7-DQ0.
97,98,100,
1,3,4,6,7,
60,61,63,
64,68,69,
71,72,9,
10,12,13,
17,18,20,
21,74,75,
77, 78,80,
81, 83, 84
DQ0-
DQ31
Input/
Output
Data I/O: The DQ0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also
serve as column/byte mask inputs during Block Writes.
30,36-45,
52,86-95
NC
-
No Connect: These pins should be left unconnected.
58
NC/Vref
-/Input No connect/Input Voltage Reference : It must be unconnected when the LVTTL
interface is used in the SGRAM. It must be applied to Vref (1.5V) when the SSTL-3
interface is used in the SGRAM.
2,8,14,22,
59,67,73,
79
V
DDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
5,11,19,
62,70,76,
82,99
V
SSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
15,35,65,
96
V
DD
Supply Power Supply: +3.3V
16,46,66,
85
V
SS
Supply Ground
0.3V
Document:1G5-0145
Rev.1
Page 6
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
Note: 1. V = Valid X = Don't Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Command
State
CKEn-1 CKEn DQM
(7)
BS
A9
A0-8
CS
RAS CAS
WE
DSF
BankActivate & Masked Write Disable
Idle
(3)
H
X
X
V
V
V
L
L
H
H
L
BankActivate & Masked Write Enable
Idle
(3)
H
X
X
V
V
V
L
L
H
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
L
Write
Active
(3)
H
X
X
V
L
V
L
H
L
L
L
Block Write Command
Active
(3)
H
X
X
V
L
V
L
H
L
L
H
Write and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
L
L
Block Write and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
L
H
Read
Active
(3)
H
X
X
V
L
V
L
H
L
H
L
Read and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
H
L
Mode Register Set
Idle
H
X
X
V
L
V
L
L
L
L
L
Special Mode Register Set
Idle
(5)
H
X
X
X
X
V
L
L
L
L
H
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
X
Burst Stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
L
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
L
SelfRefresh Exit
Idle
(SelfRefresh)
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
X
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any
(6)
H
L
X
X
X
X
H
X
X
X
X
L
H
H
H
L
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
(Power-
Down)
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
L
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
X
Data Write/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
X
Document:1G5-0145
Rev.1
Page 7
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Commands
1 BankActivate & Masked Write Disable command
(RAS = "L", CAS = "H", WE = "H", DSF = "L", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By
latching the row address on A0 to A9 at the time of this command, the selected row access is initiated.
The read or write operation in the same bank can occur after a time delay of t
RCD
(min.) from the time of
bank activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by t
RC
(min.).
The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce
chip area, therefore it restricts the back-to-back activation of both banks. t
RRD
(min.) specifies the mini-
mum time required between activating different banks. After this command is used, the Write command
and the Block Write command perform the no mask write operation.
CLK
ADDRESS
Bank A
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
Row Addr.
Bank A
Col Addr.
Bank A
Row Addr.
Bank A
Row Addr.
COMMAND
Bank A
Activate
R/W A with
AutoPrecharge
Bank B
Activate
Bank A
Activate
NOP
NOP
NOP
NOP
AutoPrecharge
Begin
RAS Cycle time (t
RC
)
RAS-CAS delay (t
RCD
)
RAS-RAS delay time (t
RRD
)
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS Latency = 3)
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS = "L", CAS = "H", WE = "H", DSF = "H", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this command is
performed, the Write command and the Block Write command perform the masked write operation. In
the masked write and the masked block write functions, the I/O mask data that was stored in the write
mask register is used.
3 BankPrecharge command
(RAS = "L", CAS = "H", WE = "L", DSF = "L", BS = Bank, A9 = "L", A0-A8 = Don't care)
The BankPrecharge command precharges the bank designated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t
RAS
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by t
RAS
(max.). Therefore, the precharge function must be performed in
any active bank within t
RAS
(max.). At the end of precharge, the precharged bank is still the idle state and
ready to be activated again.
4 PrechargeAll command
(RAS = "L", CAS = "H", WE = "L", DSF = "L", BS = Don't care, A9 = "H", A0-A8 = Don't care)
The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in
the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle
state.
5 Read command
(RAS = "H", CAS = "L", WE = "H", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address, A8 = Don't care)
Document:1G5-0145
Rev.1
Page 8
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
The Read command is used to read burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least t
RCD
(min.) before Read command is issued.
During read bursts, the valid data-out element from the starting column address will be available
following the CAS latency after the issue of Read command. Each subsequent data-out element will
be valid by the next positive clock edge (refer to the following figure). The DQs goes into high-imped-
ance at the end of the burst, unless other command was initiated. The burst length, burst sequence,
and CAS latency are determined by the mode register which is already prgrammed.A full-page burst
will continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
READ A
T0
T1
T2
T3
CAS Iatency = 1
T4
T5
T6
T7
T8
NOP
t
CK1
,DQ's
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
CAS Iatency = 2
t
CK2
,DQ's
CAS Iatency = 3
t
CK3
,DQ's
The read data appears on the DQs subjects to the values on the DQM inputs two clocks early (i.e.
DQM latency is two clocks for output buffers). A read burst without auto precharge function may be
interrupted by a subsequent Read or Write/Block Write command to the same bank or the other
active bank before the end of burst length. It may be interrupted by a BankPrecharge/PrechargeAll
command to the same bank too. The interrupt comes from Read command can occur on any clock
cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS Iatency = 1
READ B
t
CK1
,DQ's
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
CAS Iatency = 2
t
CK2
,DQ's
CAS Iatency = 3
t
CK3
,DQ's
DOUT B
3
DOUT B
3
DOUT B
3
The DQM inputs are used to avoid I/O contention on DQ pins when the interrupt comes from
Write/Block Write command. The DQMs must be asserted (High) at least two clocks prior to the
Write/Block Write command to suppress data-out on DQ pins. To guarantee DQ pins against the I/O
contention, a single cycle with high-impedance on DQ pins must occur between the last read data
and the Write/Block Write command (refer to the following three figures). If the data output of burst
read occurs at the second clock of burst write, the DQMs must be asserted (High) at least one clock
prior to the Write/Block Write command to avoid internal bus contention.
Document:1G5-0145
Rev.1
Page 9
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
Read to Write interval (Burst Length
Y
4, CAS Latency = 3)
DQM
DOUT A
0
DQ's
DINB
0
DINB
1
DINB
2
: "H" or "L"
Must be Hi-Z before
the Write Command
CLK
COMMAND
NOP
NOP
BANK A
NOP
READ A
WRITE A
NOP
NOP
NOP
Read to Write interval (Burst Length
Y
4, CAS Latency = 1, 2)
DQM
DIN A
0
DIN A
1
DIN A
2
DIN A
3
: "H" or "L"
Must be Hi-Z before
the Write Command
DIN A
0
DIN A
1
DIN A
2
DIN A
3
CAS Iatency = 1
t
CK1
,DQ's
CAS Iatency = 2
t
CK2
,DQ's
ACTIVATE
CLK
COMMAND
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
Read to Write interval (Burst Length
Y
4, CAS Latency = 1, 2)
DQM
DIN B
0
DIN B
1
DINB
2
DIN B
3
: "H" or "L"
Must be Hi-Z before
the Write Command
DIN B
0
DIN B
1
DIN B
2
DIN B
3
CAS Iatency = 1
t
CK1
,DQ's
CAS Iatency = 2
t
CK2
,DQ's
READ A
DOUT A
0
NOP
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
1 Clk Interval
Document:1G5-0145
Rev.1
Page 10
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
CAS Iatency = 1
t
CK1
,DQ's
CAS Iatency = 2
t
CK2
,DQ's
Bank
Bank(s)
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
COMMAND
READ A
NOP
NOP
Precharge
NOP
NOP
NOP
CAS Iatency = 3
t
CK3
,DQ's
Col A
Bank
Row
NOP
Activate
6 Read and AutoPrecharge command
(RAS = "H", CAS = "L", WE = "H", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address,
A8 = Don't care
)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command can not occur within a time delay of
{t
RP
(min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto pre-
charge function is ignored.
7 Write command
(RAS = "H", CAS = "L", WE = "L", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address,
A8 = Don't care
)
The Write command is used to write burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data ele-
ments will be registered on each successive positive clock edge (refer to the following figure). The DQs remains
high-impedance at the end of the burst, unless other command was initiated. The burst length and burst
sequence are determined by the mode register which is already programmed. A full-page burst will continue
until terminated (at the end of the page it will wrap to column 0 and continue).
t RP
Read to Precharge (CAS Latency = 1, 2, 3)
CLK
COMMAND
NOP
DQ0 - DQ3
DIN A
0
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DIN A
1
DIN A
3
DIN A
2
don't care
The first data element and the write
T0
T1
T2
T3
T4
T5
T6
T7
T8
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a
masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the
data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte
basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram.
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Q
DSF
BankActivate
command
MR7
MR6
MR5
MR4
MR3
MR1
MR0
MR2
D
CK
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CELL
DRAM
0 = Masked
Note: Only lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without auto precharge function may be interrupted by a subsequent Write/Block
Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt
comes from Write/Block Write command can occur on any clock cycle following the previous Write
command ( refer to the following figure).
DQM0
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DIN B
2
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
DIN B
3
1 Clk Interval
DIN A
0
DIN B
0
DIN B
1
DQ's
The Read command that interrupts a write burst without auto precharge function should
be issued one cycle after the clock edge at which the last data-in element is registered. In
order to avoid data contention, input data must be removed from the DQs at least one clock
cycle before the first read data appears on the outputs (refer to the following figure). Once the
Read command is registered, the data inputs will be ignored, and writes will not be executed.
1 = Not Masked
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
WRITE A
NOP
NOP
NOP
NOP
READ B
NOP
NOP
NOP
DIN A
0
DIN A
0
DIN A
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
CAS latency = 1
t
CK1
,DQ's
CAS latency = 2
t
CK3
,DQ's
CAS latency = 3
t
CK2
,DQ's
don't care
don't care
don't care
Input data for the write is masked
Input data must be removed from DQ' s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without auto pre-
charge function should be issued m cycles after the clock edge at which the last data-in element
is registered, where m equals t
WR
/t
CK
rounded up to the next whole number. In addition, the
DQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll com-
mand is entered (refer to the following figure).
NOP
CLK
DQ
DQM
WRITE
NOP
NOP
NOP
Precharge
Activate
COMMAND
BANK
COLn
BANK (S)
ROW
DIN
n
DIN
n+1
t
RP
ADDRESS
:don't care
Write to Precharge
t
WR
When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the
read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8 Block Write command
(RAS = "H" , CAS = "L" , WE = "L", DSF = "H" , BS =Bank , A9 = "L" , A3-A7 = Column Address, DQ0-DQ31
= Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A single
data value, which was previously loaded in the Color register, is written to the block of eight consecutive col-
umn locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with
the Block Write command is used to mask specific column/byte combinations within the block . The mapping
of the DQ inputs to the column/byte combinations is shown in following table.
T0 T1 T2 T3 T4 T5 T6
DOUT B
0
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
DQ
inputs
Column Address
DQ Planes
Controlled
DQ
Inputs
Column Address
DQ Planes
Controlled
A2
A1
A0
A2
A1
A0
DQ0
0
0
0
0~7
DQ16
0
0
0
16~23
DQ1
0
0
1
0~7
DQ17
0
0
1
16~23
DQ2
0
1
0
0~7
DQ18
0
1
0
16~23
DQ3
0
1
1
0~7
DQ19
0
1
1
16~23
DQ4
1
0
0
0~7
DQ20
1
0
0
16~23
DQ5
1
0
1
0~7
DQ21
1
0
1
16~23
DQ6
1
1
0
0~7
DQ22
1
1
0
16~23
DQ7
1
1
1
0~7
DQ23
1
1
1
16~23
DQ8
0
0
0
8~15
DQ24
0
0
0
24~31
DQ9
0
0
1
8~15
DQ25
0
0
1
24~31
DQ10
0
1
0
8~15
DQ26
0
1
0
24~31
DQ11
0
1
1
8~15
DQ27
0
1
1
24~31
DQ12
1
0
0
8~15
DQ28
1
0
0
24~31
DQ13
1
0
1
8~15
DQ29
1
0
1
24~31
DQ14
1
1
0
8~15
DQ30
1
1
0
24~31
DQ15
1
1
1
8~15
DQ31
1
1
1
24~31
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following diagram. The DQM and Mask reg-
ister masking operates as for normal Write command, with the exception that the mask information
is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is written only if
a "0" was registered for the corresponding DQM input, a "1" was registered for the corresponding DQ
signal, and the corresponding bit in the Mask register is "1".
A block write access requires a time period of t
BWC
to execute, so in general, there should be
m NOP cycles, m equals (t
BWC
-t
CK
) /t
CK
rounded up to the next whole number, after the Block Write
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank, t
BPL
must be met.
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A9,
and BS registered
coincident with BankActivate
Command)
Column Mask
on the DQ
inputs
(registered
coincident
with Block
Write Command
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMO
D Q
CK
DSF
BankActivate
command
MR0
Note: Only lower byte is shown. The operation is identical for other bytes.
Block-Write Masking Block Diagram
MR1
MR2
MR3
MR4
MR5
MR6
MR7
Mask Register
(previously loaded
from corresponding
DQ inputs
C
R
0
C
R
1
C
R
2
C
R
3
C
R
4
C
R
5
C
R
6
C
R
7
Document:1G5-0145
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
t
ck2
,DQ's
10 Block Write and AutoPrecharge command
(RAS = "H" , CAS = "L" , WE = "H", DSF = "H" , BS = Bank , A9 = "H" , A3-A7 = Column Address,
A8
= Don't care
DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically after
the block write operation. Once this command is given, any subsequent command can not occur within a
time delay of {t
BPL
+ t
RP
(min.)}.
11 Mode Register Set command
(RAS = "L" , CAS = "L", WE = "L" , DSF = "L" , BS , A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The Mode
Register Set command programs the values of CAS latency. Addressing Mode and Burst Length in the
Mode register to make SGRAM useful for variety of different applications. The default values of the Mode
Register after power-up are undefined, therefore this command must be issued at the power-up
sequence. The state of pins A0-A9 and BS in the same cycle is the data written in the mode register. One
clock cycle is required to complete the write in the mode register (refer to the following figure ). The mode
register contents can be changed using the same command and the clock cycle requirements during
operation as long as both banks are in the idle state.
NOP
T0
T1
T2
T3
T4
T5
T6
CLK
NOP
NOP
COMMAND
CAS latency = 1
T7
T8
NOP
NOP
NOP
Write A
Auto Precharge
NOP
Bank A
Activate
DIN A
0
DIN A
1
DIN A
0
DIN A
1
DIN A
0
DIN A
1
t
DAL
t
DAL
t
DAL
*
*
*
*
CAS latency = 2
t
DAL
= t
WR
+ t
RP
Begin AutoPrecharge
Bank can be reactivated at completion of t
DAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS Latency = 1, 2, 3)
9 Write and AutoPrecharge command (refer to the following figure)
(RAS = "H" , CAS = "L" , WE = "L" , DSF="L" , BS = Bank, A9 = "H", A0-A7 = Column Address,
A8 =
Don't care
)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {burst length + t
WR
+ t
RP
(min.)}. At full-page burst, only write operation is performed in
this command and the auto precharge function is ignored.
t
ck1
,DQ's
CAS latency = 3
t
ck3
,DQ's
Document:1G5-0145
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VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T10
T9
t
CK
2
Clock min
CKE
CLK
CS
RAS
CAS
WE
DSF
BS
A9
A0-A8
DQM
DQ
Address key
Hi-Z
t
RP
PrechargeAll
Mode Register
Set Command
Any
Command
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
Mode Register Set Cycle (CAS Latency = 1, 2, 3)
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page. But, lnterleave Mode only supports
burst length of 4 and 8.
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n+m), in the
table is larger than 255, only the least significant 8 bits are effective.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in following table.
CAS Latency Field (A6 ~ A4)
This field specifies the number of clock cycles from the assertion of the Read command
to the first read data. The minimum value of CAS Latency depends on the frequency of
CLK. And this value satisfying the following formula must be programmed into this field.
t
CAC (min)
CAS Latency x t
CK
A3
Addressing Mode
0
Sequential
1
Interleave
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
Burst Length
Data n
Column Address
Burst Length
Data 0
A7 A6 A5 A4 A3 A2 A1 A0
Data 1
A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A7 A6 A5 A4 A3 A2 A1 A0
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
1 clock
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
2 words:
4 words
:
8 words:
Full Page: Column address is repeated until terminated.
4 Words
8 Words
Document:1G5-0145
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Mode field (A8~A7)
A7 and A8 must be programmed to "00" in normal operation.
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
x
Vendor Use Only
Single Write Mode (A9)
This bit is used to select the write mode. When the A9 bit is "0", Burst Read and Burst Write mode is
selected. When the A9 bit is "1", Burst Read and Single Write mode is Selected.
A9
Single Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
12 Special Mode Register Set command
(RAS = "L", CAS = "L", WE = "L", DSF = "H", BS, A0-A9 = Register Data)
The special mode register is used to load the Color and Mask registers, which are used in Block
Write and masked Write cycles. The control information being written to the Special Mode register is
applied to the address inputs and the data to be written to either the Color register or the Mask register is
applied to the DQs. When A6 is "high" during a Special Mode Register Set cycle, the Color register will be
loaded with the data on the DQs. Similarly, when A5 is "high" during a Special Mode Register Set cycle,
the Mask register will be loaded with the data on the DQs. A6 = A5 = 1 in the Special Mode Register Set
cycle is illegal.
On
e clock cycle is required to complete the write in the Special Mode register. This command can
be issued at the active state. As in write operation, this command accepts the data needed through DQ
pins. Therefore it should be attended not to induce bus contention.
13 No-Operation command
(RAS = "H", CAS = "H", WE = "H")
The No-Operation command is used to perform a NOP to SGRAM which is selected (CS is Low).
This prevents unwanted commands from being registered during idle or wait states.
14 Burst Stop command
(RAS = "H", CAS = "H", WE = "L', DSF = "L")
Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is
only effective in a read/write burst without auto precharge function. The terminated read burst ends after
a delay equal to the CAS latency (refer to the following figure). The termination of a write burst is shown
in the following figure.
Functions
BS
A9~A7
A6
A5
A4~A0
Leave Unchanged
X
X
0
0
X
Load Mask Register
X
X
0
1
X
Load Color Register
X
X
1
0
X
Illegal
X
X
1
1
X
Document:1G5-0145
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS Iatency = 1
NOP
t
CK1
,DQ's
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
Termination of a Burst Write Operation (Burst Length > 4, CAS Latency = 1, 2, 3)
CAS Iatency = 2
t
CK2
,DQ's
CAS Iatency = 3
t
CK3
,DQ's
The burst ends after a delay equal to the CAS latency.
CLK
COMMAND
Burst Stop
CAS latency = 1, 2, 3
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DIN A
0
DIN A
2
DIN A
1
don't care
T0
T1
T2
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS Latency = 1, 2, 3)
DQ's
15 Device Deselect command
(CS = "H")
The Device Deselect command disables the command decoder so that the RAS, CAS, WE
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is sim-
ilar to the No Operation command.
16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS = "L", CAS = "L", WE = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SGRAM and is anala-
gous to CAS-before-RAS(CBR) Refresh in conventional DRAMs. This command is non-persis-
tent, so it must be issued each time a refresh is required. The addressing is generated by the
internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh
command. The internal refresh counter increments automatically on every auto refresh cycle to
all of the rows. The refresh operation must be performed 2048 times within 32ms. The time
required to complete the auto refresh operation is specified by t
RP
(min.). To provide the AutoRe-
fresh command, both banks need to be in the idle state and the device is not in power down
mode (CKE is high in the previous cycle). This command must be followed by NOPs until the
auto refresh operations is completed. The precharge time requirement, t
RP
(min.). must be met
befor successive auto refresh operations are performed.
17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS = "L", CAS = "L", WE = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered,
all the inputs to the SGRAM becomes "don't care" with the exception of CKE, which must remain
LOW. The refresh addressing and timing is internally generated to reduce power comsumption.
The SGRAM may remain in SelfRefresh mode for an indefinite period. Once the SGRAM enters
the SelfRefresh mode , t
RAS
(min.) is required before exit from SelfRefresh mode. The SelfRe-
fresh mode is exited by restarting the external clock and then asserting high on CKE(SelfRefresh
Exit command).
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
18 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H", WE = "H")
The command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for t
RC
(min), because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are per-
formed during normal operation, a burst of 1024 auto refresh cycles should be completed just prior to
entering, and just after exiting the SelfRefresh mode.
19 Clock Suspend Mode Entry/PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = "L")
When SGRAM operating the burst cycle, the internal CLK is suspended (masked) from the sub-
sequent cycle by issuing this command (asserting CKE "low"). The device operation is held intact
while CLK is suspended. On the other hand, when both banks are in the idle state, this command per-
forms entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned
off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state
longer than the refresh period (16ms) since the command does not perform any refresh operations.
20 Clock Suspend Mode Exit/PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = "H")
When the internal CLK has been suspended, the operation of the internal CLK is resumed from
the subsequent cycle by providing this command (asserting CKE "high"). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. t
PDE
(min.) is required when the device exit from the PowerDown mode. Any subsequent com-
mands can be issued after one clock cycle from the end of this command.
21 Data Write/Output Enable, Data Mask/Output Disable command
(DQM = "L", "H")
During a write cycle, the DQM signal functions as Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the control of output buffers. DQM is also used
for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31, DQM
masks the DQ's by a byte regardless that the corresponding DQ's are in a state of write-per-bit mask-
ing or pixel masking. the byte control. The each DQM0-3 corresponds to DQ0-7, DQ8-15, DQ16-23,
DQ24-31.
Document:1G5-0145
Rev.1
Page 21
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Absolute Maximum Rating
Symbol
Item
Rating
Unit
Note
V
IN
, V
OUT
Input, Output Voltage
-0.3~VDD + 0.3
V
1
V
DD
, V
DDQ
Power Supply Voltage
-0.3~4.6
V
1
T
OPR
Operating Temperature
0~70
C
1
T
STG
Storage Temperature
-55~150
C
1
T
SOLDER
Soldering Temperature(10s)
260
C
1
P
D
Power Dissipation
1
W
1
I
OUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (Ta = 0~70C)
Note : the peak to peak AC noise on Vref may not exceed 2%. V
REF
(DC). Vtt of transmitting device
must track V
REF
of receiving device. Typically the value of V
REF
must be about 0.45 * V
DDQ
of
the transmitting device and V
REF
track Variations in V
DDQ
.
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25C)
Note: These parameters are periodically sampled and are not 100% tested.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
V
DD
Power Supply Voltage
3.0
3.3
3.6
V
2
V
DDQ
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
2
V
IH
LVTTL Input High Voltage
2.0
-
V
DD
+ 0.3
V
2
V
IL
LVTTL Input LOW Voltage
-0.3
-
0.8
V
2
V
ref
Input Reference Voltage
1.25
1.5
1.75
V
2
V
IH
SSTL Input High voltage
V
REF
+0.2
-
V
DDQ
+0.3
V
2
V
IL
SSTL Input Low Voltage
-0.3
-
V
REF
+0.2
V
2
V
TT
SSTK Teruination Voltage
V
REF
-0.1
V
V
REF
+0.1
V
2
Symbol
Parameter
Min.
Max.
Unit
C
I
Input Capacitance
-
5
pF
C
I/O
Input/Output Capacitance
-
7
pF
Document:1G5-0145 Rev.1 Page 22
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Recommended D.C. Operating Conditions (V
DD
= 3.3V 0.3V, Ta = 0 ~ 70J)
Description/test condition Symbol
-5 -6 -7 Unit Note
Min. Max. Min. Max. Min. Max.
Operating Current
, Outputs Open
Address changed once during t
CK(min)
.
Burst Length = 1
1 bank
operation
I
DD1
190 170 150
mA
3,4
Precharge Standby Current in non-power down mode
t
CK
= t
CK(min)
,
(min)
,
(min)
Input signals are changed once during 30ns.
I
DD2N
35 35 35 3
Precharge Standby Current in non-power down mode
t
CK
= ,
(min)
,
(max)
Input signals are stable
I
DD2NS
15 15 15
Precharge Standby Current in power down mode
t
CK
= t
CK
(min),
(max)
I
DD2P
2.0 2.0 2.0 3
Precharge Standby Current in power down mode
t
CK
= ,
(max)
,
(max)
I
DD2PS
2.0 2.0 2.0
Active Standby Current in non power down mode
(min)
, t
CK
= t
CK(min)
I
DD3P
4 4 4 3
Active Standby Current in power down mode
(max)
, t
CK =
t
CK(min)
, CS V
IH(min)
I
DD3N
30 30 30
Operating Current (Page Burst, and All Bank activated)
t
CCD
= t
CCD(min)
, Outputs Open, Multi-bank interleave, gapless
data
I
DD4
220 200 170 4,5
Refresh Current
(min)
I
DD5
190 170 140 3
Self Refresh Current I
DD6
1 1 1
Operating Current (Block Write)
t
CK
= t
CK(min)
, Outputs Open, t
BWC
= t
BWC(min)
I
DD7
250 230 190
Parameter Description Min. Max. Unit Note
I
IL
Input Leakage Current
(
All other pins not under test = OV)
-5 5 A
I
OL
Output Leakage Current
Output disable, (
)
-5 5 A
V
OH
LVTTL Output "H" Level Voltage
(l
OUT
= -2mA)
2.4 - V
V
OL
LVTTL Output "L" Level Voltage
(l
OUT
= 2mA)
- 0.4 V
V
OH
SSTL Output "H" Level Voltage
(l
OUT
= -16mA)
V
TT
+0.8 - V
V
OL
SSTL Output "L" Level Voltage
(l
OUT
= 16mA)
- V
TT
+0.8 V
t
R C
t
RC min
(
)
C S
V
I H
CKE
V
I H
CKE
V
I H
CLK
V
IL
CKE
V
I L
CKE
V
I L
CLK
V
IL
CKE
V
I H
CKE
V
I L
t
RC
t
RC
CKE
0.2V
0V
V
IN
V
DD
0V
V
OUT
V
DDQ
Document:1G5-0145
Rev.1
Page 23
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 3.3V
0.3V, Ta = 0~70C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.
symbol
A.C. Parameter
-5
-6
-7
unit
Min.
Max.
Min.
Max.
Min.
Max.
t
RC
Row cycle time
45
54
62
ns
t
RCD
RAS to CAS delay
15
18
20
t
RP
Precharge to refresh/row activate com-
mand
15
18
20
t
RRD
Row activate to row activate delay
10
12
14
t
RAS
Row activate to precharge time
30
100,000
36
100,000 40
100,000
t
WR
Write recovery time
1
1
1
CLK
t
CK1
Clock cycle time
CL* = 1
14
16
18
ns
t
CK2
7
8
9
t
CK3
5
6
7
t
CH
Clock high time
1.5
2
2.5
t
CL
Clock low time
1.5
2
2.5
t
AC1
Access time from CLK
(positive edge)
CL* = 1
11
13
15
t
AC2
CL* = 2
5
5
6
t
AC3
CL* = 3
4.5
5
5.5
t
T
Transition time of CLK (Rise and Fall)
0.5
10
0.5
10
0.5
10
t
CCD
CAS to CAS Delay time
1
1
1
CLK
t
OH
Data output hold time
2
2.5
2.5
ns
t
LZ
Data output low impedance
2
2
2
t
HZ1
Data output high impedance
CL = 1
3
5
3
5
3
6
t
HZ2
CL = 2
3
5
3
5
3
6
t
HZ3
CL = 3
3
5
3
5
3
5
t
IS
Data/Address/Control Input setup time
1
1
1.5
t
IH
Data/Address/Control Input hold time
1
1
1
t
SRX
Minimum CKE "High"for Self-Refresh exit
1
1
1
CLK
t
PDE
Power Down Exit set-up time
3
4
5
ns
t
RSC
(Special) Mode Register Set Cycle time
2
2
2
CLK
t
BWC
Block Write Cycle time
1
1
1
CLK
t
DAL2
Data-in to ACT Command
(CL = 2)
1clk
+t
RP
1clk+
t
RP
1clk
+t
RP
t
DAL3
(CL = 3)
1clk
+t
RP
1clk+
t
RP
1clk
+t
RP
t
BPL
Block Write to Precharge command
1
1
1
CLK
t
REF
Refresh time
32
32
32
ms
Document:1G5-0145
Rev.1
Page 24
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of t
CK
and t
RC
. Input signals are changed one time during t
CK
. Assume that there are only one read/write
cycle during t
RC
(min).
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle t
CCD
(min).
6. Power-up sequence is described in Note 11.
7. A.C. Test Conditions
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
3.3V
1.2K
870
30pF
Output
LVTTL D.C. Test Load (A)
1.4V
50
30pF
Output
ZO=50
LVTTL A.C. Test Load (B)
Document:1G5-0145
Rev.1
Page 25
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
SSTL_3 Interface
Reference Level of Output Signals (VREF)
0.45*VDDQ
Output Load
Reference to the Under Output Load
Input Signal Levels
V
REF
+ 0.4/V
REF
-0.4
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals(V
REF
)
0.45*V
DDQ
V
DDQ
V
REF
V
OUT
Device
Under
Test
V
DDQ
0.45 * V
DDQ
RS = 25 Ohms
RT1 = 50 Ohms
V
TT
= 0.45 * V
DDQ
V
REF
= 0.45 * V
DD
V
TT
= 0.45 * V
DDQ
RT2 = 50 Ohms
C
LOAD
= 30
pF
Z = 50
Ohms
V
IN
V
SS
AC Test Load Circuits (for SSTL - 3 interface) :
8. Transition times are measured between V
IH
and V
IL
. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. t
OHZ
defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)
SSTL-3 A.C. Test Load
Document:1G5-0145
Rev.1
Page 26
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Latency relationship to frequency (Unit : clock cycles)
-5 Version (Calculation with t
CK
= 5ns ~ 30ns)
-6 Version (Calculation with t
CK
= 6ns ~ 30ns)
-7 Version (Calculation with t
CK
= 7ns ~ 30ns)
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously) when all input signals are held "NOP"
state and CKE = "H", DQM = "H". The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held "high" (V
DD
levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
Clock period
(t
CK
)
t
RC
t
RP
t
RRD
t
RAS
t
RSC
t
RCD
45
15
10
30
10
15
30ns
2
1
1
1
1
1
20ns
3
1
1
2
1
1
15ns
3
1
1
2
1
1
10ns
5
2
1
3
1
2
5ns
9
3
2
6
2
3
Clock period
(t
CK
)
t
RC
t
RP
t
RRD
t
RAS
t
RSC
t
RCD
54
18
12
36
12
18
30ns
2
1
1
2
1
1
20ns
3
1
1
2
1
1
15ns
4
2
1
3
1
2
10ns
6
2
2
4
2
2
6ns
9
3
2
6
2
3
Clock period
(t
CK
)
t
RC
t
RP
t
RRD
t
RAS
t
RSC
t
RCD
62
20
12
36
14
20
30ns
3
1
1
2
1
1
20ns
4
1
1
2
1
1
15ns
5
2
1
3
1
2
10ns
7
2
2
4
2
2
7ns
9
3
2
6
2
3
Document:1G5-0145
Rev.1
Page 27
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Timing Waveforms
CLK
CKE
CS
RAS
CAS
WE
BS
A9
A0 ~ A8
DQM
DQ
t
CK2
Activate
Bank A
Command
Write with
Hi-Z
Write
Precharge
Auto Precharge
Command
RBx
CAx
RBx
CBx
CAy
RAz
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Command
Activate
Command
Bank B
Write with
Auto Precharge
Command
Activate
Command
Bank A
Bank A
Command
Bank A
Figure 1. AC Parameters for Write Timing (Burst Length = 4, CAS Latency = 2)
DSF
RAx
RAy
RBy
RBx
RAy
RAz
RBy
t
CH
t
CL
t
IS
t
IS
t
IH
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
t
IS
tIH
tIS
tRCD
tRC
tDAL
tIS
tIH
tWR
tRP
tRRD
Bank A
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Document:1G5-0145
Rev.1
Page 28
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
Figure 2. AC Parameters for Read Timing (Burst Length = 2, CAS Latency = 2)
CLK
CKE
BS
A9
A0 ~ A8
DQM
DQ
tCH tCL
tCK2
Begin Auto Precharge
Bank B
t
IH
tIS
tIS
t
IH
tIH
tIS
RAx
RBx
RAy
RAy
CBx
RBx
CAx
RAx
tRRD
tRAS
tRC
t
RCD
t
AC2
tLZ
tOH
t
AC2
tHZ
tRP
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Ax0
Bx0
Bx1
DSF
Command
CS
RAS
CAS
WE
Ax1
Document:1G5-0145
Rev.1
Page 29
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 3. Auto Refresh (CBR) (Burst Length = 4, CAS Latency = 2)
CLK
BS
A9
A0 ~ A8
DQM
DQ
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Hi-Z
Ax0
RAx
Activate
Bank A
Command
DSF
RAx
Ax1
Ax2
Ax3
CAx
Read
Bank A
Command
t
RP
t
RC
t
RC
t
CK2
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 30
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Inputs must be
stable for 200
us
Precharge All
Command
2nd Auto Refresh
Command
Hi-Z
Mode Register
Set Command
t
RP
t
RC
1st Auto Refresh
Command
Any
Command
Address Key
2 Clock min.
Minimum of 8 Refresh cycles are required
High level
is required
t
CK2
CKE
CS
RAS
CAS
WE
DSF
Figure 4. Power on Sequence and Auto Refresh (CBR)
Document:1G5-0145
Rev.1
Page 31
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
Figure 5. Self Refresh Entry & Exit Cycle
CLK
CKE
CS
RAS
CAS
BS
A0 ~ A9
WE
DSF
DQM
Hi-Z
t
IS
DQ
Self Refresh Enter
Hi-Z
Auto Refresh
Self Refresh Exit
* Note 1
* Note 2
* Note 4
t
SRX
* Note 5
t
PDE
* Note 7
t
RC(min)
* Note 6
* Note 8
* Note 8
* Note 3
Note: To Enter SelfRefresh Mode
1. CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, Minimum t
RAS
is required before exit from SelfRefresh.
Note: To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of t
SRX
.
6 .CS starts from high.
7. Minimum t
RC
is required after CKE going high to complete SelfRefresh exit.
8. 1024 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Document:1G5-0145
Rev.1
Page 32
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 6.1 Clock Suspension During Burst Read (Using CKE)
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK1
BS
RAx
RAx
CAx
Ax0
Bank A
Read
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Ax1
Ax2
Ax3
tHZ
Note: CKE to CLK disable/enable = 1 clock
Document:1G5-0145
Rev.1
Page 33
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 6.2 Clock Suspension During Burst Read (Using CKE)
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK2
DSF
RAx
RAx
CAx
Ax0
Bank A
Read
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Ax1
Ax2
Ax3
t
HZ
Note: CKE to CLK disable/enables = 1 clock
Document:1G5-0145
Rev.1
Page 34
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 6.3 Clock Suspension During Burst Read (Using CKE)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK3
DSF
RAx
RAx
CAx
Ax0
Bank A
Read
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Ax1
Ax2
Ax3
t
HZ
Note: CKE to CLK disable/enable = 1 clock
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 35
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 7.1 Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK1
DSF
RAx
RAx
CAx
DAx0
Bank A
Write
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
DAx1
DAx2
DAx3
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 36
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 7.2 Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK2
DSF
RAx
RAx
CAx
DAx0
Bank A
Write
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
DAx1
DAx2
DAx3
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 37
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 7.3 Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Clock Suspend
1 Cycle
Hi-Z
t
CK3
DSF
RAx
RAx
CAx
DAx0
Bank A
Write
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
DAx1
DAx2
DAx3
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 8. Power Down Mode and Clock Mask
(Burst Length = 4, CAS Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
A9
A0 ~ A8
DQM
DQ
Activate
Command
Power Down
Hi-Z
t
CK2
BS
RAx
RAx
CAx
Ax0
Bank A
Power Down
Mode Entry
Read
Clock Mask
Ax3
Ax1
t
IS
t
PDE
Valid
Ax2
tHZ
ACTIVE
STANDBY
Mode Exit
Command
Bank A
Start
Clock Mask
End
Precharge
Command
Bank A
Power Down
Mode Entry
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
CKE
CS
RAS
CAS
WE
DSF
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 9.1 Random Column Read (Page within same Bank)
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank A
Read
Command
Bank A
Read
RAw
RAw
CAw
RAz
CAz
CAx
CAy
Ay2
Ay3
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Az2
Az0
Az1
Az3
Aw0
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
RAz
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 40
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 9.2 Random Column Read (Page within same Bank)
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank A
Read
Command
Bank A
Read
RAw
RAz
CAz
CAx
CAy
Az2
Az0
Az1
Az3
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
CAW
Ay2
Ay3
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Aw0
RAw
Activate
Command
Bank A
RAz
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 41
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 9.3 Random Column Read (Page within same Bank)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK3
DSF
Bank A
Read
Command
Bank A
Read
Note: CKE to CLK disable/enable = 1 clock
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Ay2
Ay3
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Aw0
Activate
Command
Bank A
RAw
RAw
CAw
CAx
CAy
RAz
RAz
CAz
Az0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 10.1
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank B
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank B
DBw0
Random Column Write (Page within same Bank)
Write
Command
Bank B
Write
Command
Bank B
RBw
RBw
CBw
CBx
CBy
RBz
RBz
CBz
DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Write
Activate
Command
Bank B
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 43
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 10.2
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank B
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank B
DBw0
Random Column Write (Page within same Bank)
Write
Command
Bank B
Write
Command
Bank B
RBw
RBw
CBy
CBx
CBy
RBz
RBz
DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Write
Activate
Command
Bank B
CKE
CS
RAS
CAS
WE
CBz
Document:1G5-0145
Rev.1
Page 44
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 10.3
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK3
DSF
Bank B
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank B
DBw0
Random Column Write (Page within same Bank)
Write
Command
Bank B
Write
Command
Bank B
RBw
RBw
CBw
CBx
CBy
RBz
CBz
DBw1 DBw2 DBw3 DBx0
DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2
Write
Activate
Command
Bank B
RBz
DBx1
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 45
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 11.1
(Burst Length = 8, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank B
Precharge
Command
Bank A
Random Row Read (Interleaving Banks)
RBx
RBx
CBx
CAx
RBy
CBy
RBx
RBy
RAx
t
RP
Bx0
Bx1
Bx2 Bx3
Bx4 Bx5
Bx6
Bx7 Ax0 Ax1
Ax2 Ax3 Ax4 Ax5 Ax6
By0
By1 By2
Ax7
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
t
AC1
High
CKE
CS
RAS
CAS
WE
t
RCD
Document:1G5-0145
Rev.1
Page 46
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 11.2
(Burst Length = 8, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank B
Random Row Read (lnterleaving Banks)
RBx
RBx
CBx
CAx
RBy
CBy
RBx
RBy
RAx
Bx0
Bx1 Bx2 Bx3
Bx4 Bx5 Bx6
Bx7 Ax0
Ax1
Ax2 Ax3 Ax4 Ax5 Ax6
By0
By1
Ax7
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
High
CKE
CS
RAS
CAS
WE
t
RP
t
AC2
t
RCD
Document:1G5-0145
Rev.1
Page 47
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 11.3
(Burst Length = 8, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK3
DSF
Bank B
Random Row Read (Interleaving Banks)
RBx
RBx
CBx
CAx
RBy
CBy
RAx
RBy
RAx
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6
By0
Ax7
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
High
Precharge
Command
Bank A
CKE
CS
RAS
CAS
WE
t
RP
t
AC3
t
RCD
Document:1G5-0145
Rev.1
Page 48
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 12.1
(Burst Length = 8, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
A9
A0 ~ A8
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank A
Random Row Read (Interleaving Banks)
RAx
RAx
CAx
CBx
RAy
CAy
RBx
RAy
RBx
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
High
DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank A
CKE
CS
RAS
CAS
WE
t
RP
t
WR
t
RCD
Document:1G5-0145
Rev.1
Page 49
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 12.2
(Brust Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank A
Random Row Write (Interleaving Banks)
RAx
RAx
CAx
CBx
RAy
CAy
RBx
RAy
RBx
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
High
DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank A
DAy4
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
* t
WR >
t
WR(min.)
t
WR*
t
WR*
t
RCD
t
RP
Document:1G5-0145
Rev.1
Page 50
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 12.3
(Burst Length = 8, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK3
BS
Bank A
Random Row Write (Interleaving Banks)
RBx
RBx
CAx
CBx
RAy
CAy
RBx
RAy
RBx
t
RP
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
High
t
RCD
R*
t
W
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank A
t
WR
*
*t
WR
> t
WR
(min)
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6
DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
DAx7
DBx2
DBx0 DBx1
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 13.1
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank A
Read and Write Cycle (Burst Length = 4, CAS Latency = 1)
RAx
RAx
CAx
CAy
CAz
DAy3
The Write Data
is Masked with a
Zero Clock
Read
Command
Bank A
Write
Command
Bank A
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
Az0
Az1
Az3
Latency
The Read Data
is Masked with a
Two Clock
Latency
Read
Command
Bank A
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 52
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 13.2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank A
Read and Write Cycle (Burst Length = 4, CAS Latency = 2)
RAx
RAx
CAx
CAy
CAz
The Write Data
is Masked with a
Zero Clock
Read
Command
Bank A
Write
Command
Bank A
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Latency
The Read Data
is Masked with a
Two Clock
Latency
Read
Command
Bank A
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 53
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 13.3 Read and Write Cycle (Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK3
DSF
Bank A
RAx
RAx
CAx
CAz
The Write Data
is Masked with a
Zero Clock
Read
Command
Bank A
Write
Command
Bank A
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Latency
The Read Data
is Masked with a
Two Clock
Latency
Read
Command
Bank A
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
CAy
Document:1G5-0145
Rev.1
Page 54
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 14.1
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK1
DSF
Bank A
Interleaving Column Read Cycle
RAx
RAx
CAx
CAy
Read
Command
Bank B
Ax0
Ax1
Ax2
Ax3
Bw0
Bz2
Precharge
Command
Bank A
RBw
RBw
CBw
CBx
CBy
CBz
Bz1
Bw1
Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0
Bz1
Bz3
t
RCD
t
AC1
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank B
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 55
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 14.2
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Command
Hi-Z
t
CK2
DSF
Bank A
Interleaving Column Read Cycle
RAx
RAx
CAx
Read
Command
Bank B
Ax0
Ax1
Ax2
Ax3
Bw0
Precharge
Command
Bank A
CBw
CBx
CAy
CBy
CBz
Bw1
Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0
Bz1
Bz3
t
RCD
t
AC2
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank B
RBw
RBw
Bz2
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 56
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 14.3. Interleaved Column Read Cycle (Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
BS
DQM
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
Read
Bank A
DSF
t
CK3
RAx
RBx
Command
t
RCD
RAx
Read
Bank B
Command
Read
Bank B
Command
Read
Bank B
Command
Precharge
Bank B
Command
Read
Bank A
Command
Precharge
Bank A
Command
Ay3
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Bz1
Ay0
Ay1
Ay2
t
AC3
CAx
RBx
CBx
CBy
CBz
CAy
A9
A0 ~ A8
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 57
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 15.1. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
DQM
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
DSF
t
CK1
RAx
CBy
CBz
DAx1
DAx0
DAx2
DAx3
DBw1
DBw0
DBx0 DBx1
DBy0
DAy0 DAy1
DBy1
DBz0
DBz3
DBz2
DBz1
t
RRD
t
RCD
t
RP
t
WR
t
RP
Write
Bank A
Command
Write
Bank B
Command
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Bank B
Command
Write
Bank B
Command
Write
Bank A
Command
Write
Bank B
Command
RAx
RBw
CAx
RBw
CBw
CBx
CAy
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 58
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
BS
A9
DQM
A0 ~ A8
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
DSF
Write
Bank A
Command
Write
Bank B
Command
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Bank B
Command
Write
Bank B
Command
Write
Bank A
Command
Write
Bank B
Command
DAx1
DAx0
DAx2
DAx3
DBw1
DBw0
DBx0 DBx1
DBy0
DAy0 DAy1
DBy1
DBz0
DBz3
DBz2
DBz1
t
RCD
t
RRD
t
WR
t
RP
t
RP
CBz
CBy
CAy
CBx
CBw
RBw
CAx
RAx
RAx
RBw
t
CK2
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 59
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 15.3. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
BS
DQM
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
DSF
Write
Bank A
Command
Write
Bank B
Command
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Bank B
Command
Write
Bank B
Command
Write
Bank A
Command
Write
Bank B
Command
t
RRD
> t
RRD(min)
RAx
RBw
t
CK3
DAx1
DAx0
DAx2
DAx3
DBw1
DBw0
DBx0 DBx1
DBy0
DAy0 DAy1
DBy1
DBz0
DBz3
DBz2
DBz1
t
RCD
t
WR
t
RP
CBz
CBy
CAy
CBx
CBw
RBw
CAx
RAx
t
WR (min)
A9
A0 ~ A8
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 60
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 16.1. Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
A9
DQM
A0~A8
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
DSF
t
CK1
By1
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
Bz3
By2
By3
Bz0
Bz1
Bz2
Activate
Command
Bank B
Read
Command
Bank A
Read with
Command
Bank B
Auto Precharge
Read with
Command
Bank A
Auto Precharge
Activate
Command
Bank B
Read with
Command
Bank B
Auto Precharge
Read with
Command
Bank B
Auto Precharge
High
RBy
RBz
CBz
RBy
CAy
CBx
CAx
RAx
RBz
RAx
CAx
CBy
RBx
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Bx1
CAz
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 16.2 Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 2)
CLK
CKE
CS
RAS
CAS
DSF
BS
A9
DQM
CAx
Activate
Bank A
Command
Read with
Command
Bank A
Hi-Z
t
CK2
High
WE
RAx
RAz
RAx
RBx
RBy
RAz
RBx
CBx
RAy
RBy
CBy
Ax0
Ax1 Ax2 Ax3 Bx0
Bx2 Bx3
Ay0
Ay1 Ay2 Ay3
By0
By1
By2
Az2
By3
Az0 Az1
Activate
Bank B
Command
Read with
Command
Bank B
Auto Precharge
Read with
Command
Bank A
Auto Precharge
Activate
Bank B
Command
Read with
Command
Bank B
Auto Precharge
Activate
Bank A
Command
Read with
Command
Bank A
Auto Precharge
A0 ~ A8
DQ
Document:1G5-0145
Rev.1
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VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
RBx
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 16.3 Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 3)
BS
A9
DQM
CAx
A0 ~ A8
Activate
Bank A
Command
Activate
Command
Bank B
Read
Command
Bank A
Hi-Z
t
CK3
RAx
RBx
RBy
RAx
CBx
CAy
RBy
CBy
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
BY2
BY1
BY0
Activate
Bank B
Command
Read with
Command
Bank B
Auto Precharge
High
DSF
BY3
Read with
Command
Bank B
Auto Precharge
Read with
Command
Bank A
Auto Precharge
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 63
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 17.1 Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 1)
BS
A9
DQM
RAx
CAx
A0 ~ A8
DQ
Activate
Bank A
Command
Activate
Command
Bank B
Write with
Command
Bank B
Hi-Z
Write
Command
Bank A
t
CK1
High
RAx
RBx
RAz
RBy
RBx
CBx
CAy
RBy
CBy
CAz
RAz
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3
DAz0
DAz3
DAz2
DAz1
Activate
Bank B
Command
Activate
Bank A
Command
Auto Precharge
Write with
Command
Bank A
Auto Precharge
Write with
Command
Bank B
Auto Precharge
Write with
Command
Bank A
Auto Precharge
CLK
CKE
CS
RAS
CAS
WE
DSF
Document:1G5-0145
Rev.1
Page 64
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 17.2. Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 2)
BS
A9
DQM
A0 ~ A8
Write
Command
Bank A
t
CK2
High
RAx
RBx
RBy
RAz
RAx
CAx
CBx
CAy
RBy
RBx
CBy
RAz
CAz
Hi-Z
DAx1 DAx2
DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3 DAz0
DAz3
DAz2
DAz1
DAx0
Write with
Command
Bank A
Auto Precharge
Activate
Command
Bank B
Write with
Command
Bank B
Auto Precharge
Activate
Bank A
Command
Activate
Bank B
Command
Activate
Bank A
Command
Write with
Command
Bank B
Auto Precharge
Write with
Command
Bank A
Auto Precharge
CLK
CKE
CS
RAS
CAS
WE
DQ
DSF
Document:1G5-0145
Rev.1
Page 65
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 17.3. Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 3)
BS
A9
DQM
A0 ~ A8
DQ
t
CK3
DSF
High
RAx
CAx
CBx
RBx
RBy
CBy
Hi-Z
DAx1 DAx2
DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
DAx0
Write with
Command
Bank A
Auto Precharge
Activate
Command
Bank B
Write with
Command
Bank B
Auto Precharge
Activate
Bank A
Command
Activate
Bank B
Command
Write with
Command
Bank B
Auto Precharge
RAx
RBx
RBy
CAy
Write
Command
Bank A
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 66
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 18.1. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
BS
DQM
DQ
High
Hi-Z
Command
Burst Stop
Read
Command
Bank B
Activate
Command
Bank B
t
CK1
RBx
CBx
RBx
RBy
RBy
RAx
CAx
RAx
Ax+1
Ax+2
Ax-2
Ax-1
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Ax
Bx+5
Bx+6
Bx+7
Ax
t
RP
t
RRD
Activate
Command
Bank B
Activate
Bank A
Command
Read
Command
Bank A
Precharge
Bank B
Command
Full Page burst operation does not
The burst counter wraps
from the highest order
page address back to zero
during this time interval
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 67
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 18.2. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 2)
Activate
Bank A
Command
Activate
Command
Bank A
Hi-Z
Read
Bank A
t
CK2
High
RAx
RBx
RBy
RAx
CAx
RBx
CBx
RBy
Ax
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Bx+5
Bx+6
Command
Read
Bank B
Command
Precharge
Burst Stop
Command
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not terminate
when the burst length is satisfied; the burst
counter increments and continues bursting
beginning with the starting address.
t
RP
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 68
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 18.3. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 3)
Activate
Bank A
Command
Activate
Command
Bank B
Hi-Z
Read
Bank A
t
CK3
High
RAx
RBx
RBy
Ax
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Bx+5
Command
Precharge
Burst Stop
Command
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not terminate
when the burst length is satisfied; the burst
counter increments and continues bursting
beginning with the starting address.
t
RP
RAx
CAx
RBx
CBx
RBy
Read
Bank B
Command
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 69
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
RBx
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 19.1 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 1)
t
CK1
RAx
RBx
RAx
CAx
CBx
Activate
Bank A
Command
Activate
Command
Bank B
Activate
Command
Bank B
DAx
DAx+1
DBx
DBx+1 DBx+2
Write
Command
Bank B
Data is
ignored
High
RBy
DAx+1
DAx
DAx+2 DAx+3 DAx-1
DBx+7
DBx+3 DBx+4 DBx+5 DBx+6
Hi-Z
Write
Command
Bank A
Precharge
Command
Bank B
Burst Stop
Command
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
increments and continues bursting
beginning with the starting address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
RBy
Document:1G5-0145
Rev.1
Page 70
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
DBx+6
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate
Command
t
CK2
Write
Command
RAx
RAx
CAx
RBy
CBx
RBy
DAx
DAx-1
DAx+3
DAx+2
DAx+1
Bank B
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
High
RBx
RBx
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Write
Command
Bank B
Activate
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
Data is ignored
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Figure 19.2 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 2)
Document:1G5-0145
Rev.1
Page 71
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure19.3 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 3)
Activate
Command
t
CK3
Write
Command
RAx
CAx
Bank A
Bank A
Activate
Command
Bank B
High
RAx
RBx
CBx
RBy
Precharge
Command
Bank B
RBy
DAx
DAx-1
DAx+3
DAx+2
DAx+1
DAx
DAx+1
DBx
DBx+1 DBx+2
DBx+3
DBx+4 DBx+5
Data is ignored
Activate
Command
Bank B
Burst stop
Command
Write
Command
Bank B
The burst counter wraps
from the highest order
page addresss back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
inrements and continues bursting
beginning with the starting address.
Hi-Z
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
RBx
Document:1G5-0145
Rev.1
Page 72
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 20. Byte Write Operation (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
Activate
Command
Hi-Z
t
CK2
BS
Bank A
Ax1
Ax0
Ax2
Write
Command
Bank A
DSF
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
RAx
CAx
CAy
CAz
RAx
DAy1
Az1
Az2
Ax2
Ax1
Ax3
Az3
DAy2
DAy0 DAy1
DAy3
Az2
Az0
Az1
Read
Command
Bank A
Upper 3 Bytes
are masked
Lower Byte
is masked
Upper 3 Bytes
are masked
Read
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
High
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 73
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 21. Burst Read and Single Write Operation (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
Activate
Command
Hi-Z
t
CK2
BS
Bank A
DSF
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
Read
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
High
RAx
RAx
CAx
CAw
CAy
CAz
Ax0
Ay1
Ay3
Az0
Ax1
Ax2
Ax3
DQw0
DQx0
Ay0
Az0
DQw0
Ay3
Ay2
Ax0
Ay0
Upptr 3 Bytes
Read
Command
Bank A
Single Write
Bank A
Command
Single Write
Bank A
Command
Single Write
Bank A
Command
CAx
Hi-Z
Ax1
Ax2
Ax3
A9
A0 ~ A8
is masked
Document:1G5-0145
Rev.1
Page 74
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 22. Full Page Burst Read and Single Write Operation
Activate
Command
Bank A
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
Read
Command
Bank A
Read
Command
Bank A
Single Write
Bank A
Command
Single Write
Bank A
Command
(Burst Length = Full Page, CAS Latency = 3)
Burst Stop
Command
Burst Stop
Command
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
t
CK3
BS
DSF
DQM0
High
RAv
RAv
CAv
CAw
CAx
CAy
Av0 Av1 Av2 Av3
DQw0
DQx0
Av0 Av1 Av2 Av3
Av0 Av1 Av2 Av3
DQw0
DQx0
Av0 Av1 Av2 Av3
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 75
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 23. Random Row Read (lnterleaving Banks)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CK1
t
High
RBu
RAv
RBw
RBx
RAx
RBy
RAy
RBz
RAz
RBu
RAu
RBv
RAW
CBu
RAu
CAu
RBv
CBv
RAv
CAv
RBw
CBw
RAw
CAw
RBx
RAx
CBx
CAx
RBy
RAy
RBz
CBy
CAy
RAz
CBz
Bu0
Au0
Bu1
Au1
Bv0
Bw0
Bx0
By0
Bx1
Av0
Aw0
Ay0
Aw1
Ax0
Bv1
Av1
Bw1
Ax1
By1
Ay1
Bz0
RP
t
RP
t
RP
t
RP
t
RP
t
RP
t
RP
t
RP
t
RP
t
RP
t
Activate
Command
Bank B
Activate
Command
Bank A
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Read
Bank B
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Begin Auto
Bank B
Precharge
Begin Auto
Bank A
Precharge
Begin Auto
Bank B
Precharge
Begin Auto
Bank B
Precharge
Begin Auto
Bank B
Precharge
Begin Auto
Bank B
Precharge
Begin Auto
Bank A
Precharge
Begin Auto
Bank A
Precharge
Begin Auto
Bank A
Precharge
Begin Auto
Bank A
Precharge
(Burst Length = 2, CAS Latency = 1)
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 76
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 24. Full Page Random Column Read
(Burst Length = Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CK2
t
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
RAx
RAx
CAx
CBx
RBx
CAy
CBy
CAz
CBz
Az0
Az1
Bz0
Bx0
By0
Bz2
Ay0
Ax0
Bz1
By1
Ay1
Az2
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Termination)
RBx
RBw
RBw
t
RP
t
RCD
t
RRD
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 77
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 25. Full Page Random Column Write (Burst Length = Full Page, CAS Latency = 2)
t
CK2
RAx
RBx
RBw
RAx
CBz
CAz
RBw
RBx
CAx
CBx
CAy
CBy
t
RP
t
WR
Activate
Bank A
Command
Activate
Command
DBx0
Bank B
DAx0
Activate
Command
Bank B
DAy0
DAy1
DBy0
DBy1
DAz0
DAz1
DAz2
DBz0
DBz1
DBz2
Write
Command
Bank A
Precharge
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank A
Command Bank B
(Precharge Termination)
Write Data
is masked
Write
Command
Bank B
t
RCD
t
RRD
BS
DQM
DQ
A9
A0 ~ A8
DSF
CLK
CKE
CS
RAS
CAS
WE
Document:1G5-0145
Rev.1
Page 78
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 26.1. Precharge Termination of a Burst (Burst Length = Full Page, CAS Latency = 1)
CLK
CKE
CS
RAS
CAS
WE
BS
DQM
DQ
Activate
Command
t
CK1
DSF
Write
Command
RAx
RAx
CAx
RAy
CAy
RAz
RAy
RAz
CAz
t
WR
t
RP
t
RP
DAx4
DAx3
DAx2
DAx1
DAx0
Ay0
Ay1
Ay2
DAz0
DAz6
DAz7
DAz1
DAz2
DAz3
DAz4
DAz5
Bank A
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Activate
Command
Bank A
Read
command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Command
Write
Bank A
Precharge
Termination of
a Read Burst
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 79
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Figure 26.2. Precharge Termination of a Burst
CLK
CKE
CS
RAS
CAS
WE
BS
DQM
DQ
Activate
Command
t
CK2
DSF
Write
Command
RAx
CAx
RAy
t
WR
t
RP
t
RP
DAx3
DAx2
DAx1
DAx0
Ay0
Ay1
DAz0
DAz1
DAz2
Bank A
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Activate
Command
Bank A
Read
command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Termination of
a Read Burst
(Burst Length = 8 or Full Page, CAS Latency = 2)
High
RAz
RAx
RAy
CAy
RAz
CAz
t
RP
Ay2
Read
Command
Bank A
Precharge
Command
Bank A
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 80
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Figure 26.3 Precharge Termination of a Burst
(Burst Length = 4, 8 or Full page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
DQM
DQ
Activate
Command
t
CK3
DSF
RAx
CAx
Bank A
Read
Command
Bank A
High
RAx
RAy
RAz
RAy
CAy
RAz
DAx0 DAx1
Ay0
Ay1
Ay2
t
RP
t
RP
Write
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked
Precharge Termination
of a Write Burst
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst
t
WR
A9
A0 ~ A8
Document:1G5-0145
Rev.1
Page 81
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Ordering Information
Part Number
Frequency
Package
Packing Type
VG4616321BQ-7
143MHz
QFP
Tray
VG4616321BQ-7R
143MHz
QFP
Tape & Reel
VG4616321BQ - 6
166MHz
QFP
Tray
VG4616321BQ - 6R
166MHz
QFP
Tape & Reel
VG4616321BQ - 5
200MHz
QFP
Tray
VG4616321BQ - 5R
200MHz
QFP
Tape & Reel
VG4616322BQ-7
143MHz
QFP
Tray
VG4616322BQ-7R
143MHz
QFP
Tape & Reel
VG4616322BQ-6
166MHz
QFP
Tray
VG4616322BQ-6R
166MHz
QFP
Tape & Reel
VG4616322BQ-5
200MHz
QFP
Tray
VG4616322BQ-5R
200MHz
QFP
Tape & Reel
VG4616321BQ - 7
VG
46
16321(2)
B
Q
7
R
VIS Memory Product
Synchronous Graphic
Sync, 2k self - ref. 512k x 32 SGRAM.16321 LVTTL, 16322 : SSTL-3
Revision
Package Type (Q : QFP)
Speed (7 : 7ns, 6 : 6ns , 5 : 5ns)
Packing Type (R : Tape & Reel, Blank : Tray)
Document:1G5-0145
Rev.1
Page 82
VIS
VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary CMOS Synchronous Graphic RAM
Outline Drawing Information
DETAIL A
SEATING PLANE
e
0.08mm
e
100
1
81
80
D1
D
A2
0.12mm
31
30
E1 E
A1
M
DETAIL A
TYP.
b
L1
L
50
51
c
A
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON THE
LEAD TO BE WIDER THAN THE MAXIMUM b DIMENSION BY
2. DIMENSION D1 & E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE
1. CONTROLLING DIMENSION : MILLIMETERS
ALLOWABLE PROTRUSION IS 0.25mm PER SIDE.
DIMENSION D1 & E1 INCLUDE MOLD MISMATCH.
LOWER RADIUS OR THE FOOT.
NOTE:
14.15
17.40
20.15
23.40
0.88
0.73
L
L1
0X
---
1.60 REF.
13.85
17.00
19.85
23.00
e
E1
D1
E
D
14.00
0.65 BASIC
17.20
23.20
20.00
0.11
2.50
0.22
0.25
---
A2
c
b
A1
A
2.70
0.15
---
---
---
DIM
MIN.
NOM.
MILLIMETERS
0.041
0.035
0.029
1.03
7X
0X
---
0.063 REF.
7X
0.557
0.685
0.793
0.921
0.015
0.114
---
0.134
0.009
0.026 BASIC
0.545
0.781
0.669
0.906
0.551
0.677
0.913
0.787
0.098
2.90
0.23
0.38
0.004
0.009
---
3.40
0.010
---
0.106
0.006
---
---
---
MAX.
MAX.
MIN.
NOM.
INCHES
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