The Western Design Center, Inc.
September 2003 W65C02S Data Sheet
The Western Design Center, Inc., 2003. All rights reserved
WDC
W65C02S
Microprocessor
DATA SHEET
The Western Design Center, Inc.
September 2003 W65C02S Data Sheet
The Western Design Center, Inc. W65C02S Data Sheet 2
WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible
product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been
made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to
particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each
application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing
contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of
third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of
which are available upon request.
Copyright
1981-2003 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole, or
in part, in any form.
The Western Design Center, Inc.
W65C02S Data Sheet
The Western Design Center, Inc. W65C02S Data Sheet
3
TABLE OF CONTENTS
1
INTRODUCTION................................................................................................................................................................................5
1.1
F
EATURES OF THE
W65C02S..................................................................................................................................................... 5
2
FUNCTIONAL DESCRIPTION......................................................................................................................................................6
2.1
I
NSTRUCTION
R
EGISTER
(IR)
AND
D
ECODE
........................................................................................................................... 6
2.2
T
IMING
C
ONTROL
U
NIT
(TCU) ................................................................................................................................................. 6
2.3
A
RITHMETIC AND
L
OGIC
U
NIT
(ALU) ..................................................................................................................................... 6
2.4
A
CCUMULATOR
R
EGISTER
(A)................................................................................................................................................... 6
2.5
I
NDEX
R
EGISTERS
(X
AND
Y)...................................................................................................................................................... 6
2.6
P
ROCESSOR
S
TATUS
R
EGISTER
(P) ........................................................................................................................................... 6
2.7
P
ROGRAM
C
OUNTER
R
EGISTER
(PC)....................................................................................................................................... 6
2.8
S
TACK
P
OINTER
R
EGISTER
(S) .................................................................................................................................................. 7
3
PIN FUNCTION DESCRIP TION ...................................................................................................................................................9
3.1
A
DDRESS
B
US
(A0-A15)............................................................................................................................................................... 9
3.2
B
US
E
NABLE
(BE).......................................................................................................................................................................... 9
3.3
D
ATA
B
US
(D0-D7)........................................................................................................................................................................ 9
3.4
I
NTERRUPT
R
EQUEST
(IRQB).................................................................................................................................................... 9
3.5
M
EMORY
L
OCK
(MLB) ............................................................................................................................................................... 9
3.6
N
O N
-M
ASKABLE
I
NTERRUPT
(NMIB)...................................................................................................................................... 9
3.7
N
O
C
ONNECT
(NC) ..................................................................................................................................................................... 10
3.8
P
HASE
2
I
N
(PHI2),
P
HASE
2
O
UT
(PHI2O)
AND
P
HASE
1
O
UT
(PHI1O) ...................................................................... 10
3.9
R
EAD
/W
RITE
(RWB) ................................................................................................................................................................. 10
3.10
R
EADY
(RDY) .............................................................................................................................................................................. 10
3.11
R
ESET
(RESB) ............................................................................................................................................................................. 11
3.12
S
ET
O
VERFLOW
(SOB).............................................................................................................................................................. 11
3.13
SYNC
HRONIZE WITH
O
P
C
ODE FETCH
(SYNC)................................................................................................................... 11
3.14
P
OWER
(VDD)
AND
G
ROUND
(VSS)........................................................................................................................................ 11
3.15
V
ECTOR
P
ULL
(VPB) ................................................................................................................................................................. 11
4
ADDRESSING MODES ...................................................................................................................................................................16
4.1
A
BSOLUTE A
.................................................................................................................................................................................. 16
4.2
A
BSOLUTE
I
NDEXED
I
NDIRECT
(
A
,
X
) ...................................................................................................................................... 16
4.3
A
BSOLUTE
I
NDEXED WITH
X
A
,
X
............................................................................................................................................. 16
4.4
A
BSOLUTE
I
NDEXED WITH
Y
A
,
Y
............................................................................................................................................ 17
4.5
A
BSOLUTE
I
NDIRECT
(
A
)............................................................................................................................................................ 17
4.6
A
CCUMULATOR
A ....................................................................................................................................................................... 17
4.7
I
MMEDIATE
A
DDRESSING
#....................................................................................................................................................... 17
4.8
I
MPLIED I
....................................................................................................................................................................................... 17
4.9
P
ROGRAM
C
OUNTER
R
ELATIVE R
........................................................................................................................................... 18
4.10
S
TACK S
......................................................................................................................................................................................... 18
4.11
Z
ERO
P
AGE ZP
.............................................................................................................................................................................. 18
4.12
Z
ERO
P
AGE
I
NDEXED
I
NDIRECT
(
ZP
,
X
) .................................................................................................................................. 18
4.13
Z
ERO
P
AGE
I
NDEXED WITH
X
ZP
,
X
......................................................................................................................................... 19
4.14
Z
ERO
P
AGE
I
NDEXED WITH
Y
ZP
,
Y
........................................................................................................................................ 19
4.15
Z
ERO
P
AGE
I
NDIRECT
(
ZP
)........................................................................................................................................................ 19
4.16
Z
ERO
P
AGE
I
NDIRECT
I
NDEXED WITH
Y
(
ZP
),
Y
.................................................................................................................. 19
5
OPERATION TABLES ....................................................................................................................................................................21
6
DC, AC AND TIMING CHARACTERISTICS .........................................................................................................................23
The Western Design Center, Inc.
W65C02S Data Sheet
The Western Design Center, Inc. W65C02S Data Sheet
4
6.1
DC
C
HARACTERISTICS
TA
=
-40
C
TO
+85
C
(PLCC,
QFP)
TA=
0
C
TO
70
C
(DIP) .......................................... 24
6.2
AC
C
HARACTERISTICS
TA
=
-40
C
TO
+85
C
(PLCC,
QFP)
TA=
0
C
TO
70
C
(DIP) .......................................... 25
7
CAVEATS ............................................................................................................................................................................................36
8
W65C02DB DEVELOPER BOARD AND .................................................................................................................................37
IN-CIRCUIT EMULATOR (ICE)..........................................................................................................................................................37
8.1
F
EATURES
:.................................................................................................................................................................................... 38
8.2
M
EMORY MAP
:............................................................................................................................................................................. 38
8.3
C
ROSS
-D
EBUGGING
M
ONITOR
P
ROGRAM
............................................................................................................................. 38
8.4
BUILDING................................................................................................................................................................................... 38
9
HARD CORE MODEL .....................................................................................................................................................................39
9.1
F
EATURES OF THE
W65C02S
H
ARD
C
ORE
M
ODEL
................................................................................................................. 39
10
SOFT CORE RTL MODEL ........................................................................................................................................................39
10.1
W65C02
S
YNTHESIZABLE
RTL-C
ODE IN
V
ERILOG
HDL................................................................................................. 39
TABLE OF TABLES
TABLE 3 -1 VECTOR LOCATIONS....................................................................................................................................................12
TABLE 3 -2 PIN FUNCTION TABLE..................................................................................................................................................12
TABLE 4 -1 ADDRESSING MODE TABLE......................................................................................................................................20
TABLE 5 -1 INSTRUCTION SET TABLE .........................................................................................................................................21
TABLE 5 -2 W65C02S OPCODE MATRIX ........................................................................................................................................22
TABLE 6 -1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................23
TABLE 6 -2 DC CHARACTERISTICS................................................................................................................................................24
TABLE 6 -3 AC CHARACTERISTICS ..............................................................................................................................................25
TABLE 6 -4 OPERATION, OPERATION CODES AND STATUS REGISTER.....................................................................28
TABLE 6 -5 INSTRUCTION TIMING CHART ...............................................................................................................................32
TABLE 7 -1 MICROPROCESSOR OPERATIONAL ENHANCEMENTS ..............................................................................36
TABLE OF FIGURES
FIGURE 2-1 W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM ...................................................... 7
FIGURE 2-2 W65C02S MICROPROCESSOR PROGRAMMING MODEL.................................................................................... 8
FIGURE 3-1 W65C02S 40 PIN PDIP PINOUT..................................................................................................................................... 13
FIGURE 3-2 W65C02S 44 PIN PLCC PINOUT ................................................................................................................................... 14
FIGURE 3-3 W65C02S 44 PIN QFP PINOUT ...................................................................................................................................... 15
FIGURE 6-1 IDD VS VDD....................................................................................................................................................................... 24
FIGURE 6-2 F MAX VS VDD................................................................................................................................................................. 24
FIGURE 6-3 GENERAL TIMING DIAGRAM ..................................................................................................................................... 26
The Western Design Center, Inc.
W65C02S Data Sheet
The Western Design Center, Inc. W65C02S Data Sheet
5
1
INTRODUCTION
The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the PHI2 clock
can be stopped when it is in the high (logic 1) or low (logic 0) state. The variable length instruction set and manually
optimized core size makes the W65C02S an excellent choice for low power System-on-Chip (So C) designs. The Verilog
RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for
evaluation or volume production. To aid in system development, WDC provides a Development System that includes a
W65C02DB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see
www.westerndesigncenter.com for more information.
1.1
Features of the W65C02S
8-bit data bus
16-bit address bus provides access to 65,536 bytes of memory space
8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register
16-bit Program Counter
69 instructions
16 addressing modes
212 Operation Codes (OpCodes)
Vector Pull (VPB) output indicates when interrupt vectors are being addressed
WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and
provide synchronization with external events
Variable length instruction set provides for lower power and smaller code optimization over fixed length instruction
set processors
Fully static circuitry
Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified
Low Power consumption, 150uA@1MHz
PDF 
ZIP