The Western Design Center, Inc.
May 2003 W65C22S Data Sheet
The Western Design Center, Inc., 2003. All rights reserved
WDC
W65C22S
Versatile Interface Adapter (VIA)
DATA SHEET
The Western Design Center, Inc.
W65C22S Data Sheet
The Western Design Center, Inc. W65C22S Datasheet
2
WDC reserves the right to make changes at any time without notice in order to improve design and supply the
best possible product. Information contained herein is provided gratuitously and without liability, to any user.
Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is
given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the
responsibility of the user to determine the suitability of the products for each application. WDC products are
not authorized for use as critical components in life support devices or systems. Nothing contained herein
shall be construed as a recommendation to use any product in violation of existing patents or other rights of
third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales
Policies, copies of which are available upon request.
Copyright
1981-2003 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction, in whole, or in part, in any form.
The Western Design Center, Inc.
W65C22S Data Sheet
The Western Design Center, Inc. W65C22S Datasheet
3
TABLE OF CONTENTS
1. SECTION 1 W65C22S FUNCTION DESCRIPTION ................................................................. 7
1.1.
Peripheral Data Ports ................................................................................................................ 8
1.2.
Data Transfer - Handshake Control........................................................................................ 10
1.3.
Read Handshake Control. ....................................................................................................... 11
1.4.
Write Handshake Control. ...................................................................................................... 12
1.5.
Timer 1 Operation................................................................................................................... 14
1.6.
Timer 1 One -Shot Mode ......................................................................................................... 17
1.7.
Timer 1 Free-Run Mode ......................................................................................................... 18
1.8.
Timer 2 Operation. .................................................................................................................. 19
1.9.
Timer 2 One -Shot Mode ......................................................................................................... 19
1.10.
Timer 2 Pulse Counting Mode................................................................................................ 20
1.11.
Shift Register Operation.......................................................................................................... 20
1.12.
Shift Register Input Modes..................................................................................................... 21
1.12.1
Shift Register Disabled (000) .......................................................................................................................................21
1.12.2
Shift In - Counter T2 Control (001) ............................................................................................................................21
1.12.3
Shift In - PHI2 Clock Control (010).............................................................................................................................22
1.12.1.
Shift In - External CB1 Clock Control (011)................................................................................................................23
1.13.
Shift Register Output Modes.................................................................................................. 23
1.13.1
Shift Out - Free Running at T2 Rate (100).................................................................................................................23
1.13.2
Shift Out - T2 Control (101).........................................................................................................................................24
1.13.3
Shift Out - PHI2 Clock Control (110)..........................................................................................................................24
1.13.4
Shift Out - External CB1 Clock Control (111)............................................................................................................25
1.14.
Interrupt Operation................................................................................................................. 25
2. SECTION 2 PIN FUNCTION DESCRIPTION......................................................................... 28
2.1
Peripheral Data Port A Control Lines. (CA1, CA2) ............................................................... 31
2.2
Peripheral Data Port B Control Lines. (CB1, CB2) ............................................................... 31
2.3
Chip Select (CS1, CS2B)......................................................................................................... 32
2.4
Data Bus. (D0-D7) ................................................................................................................... 32
2.5
Interrupt Request. (IRQB) ..................................................................................................... 32
2.6
Peripheral Data Port A(PA0-PA7)........................................................................................... 32
2.7
Peripheral Data Port B (PB0-PB7).......................................................................................... 33
2.8
Phase 2 Internal Clock. (PHI2)............................................................................................... 34
2.9
Reset (RESB) ......................................................................................................................... 34
2.10
Register Select. (RS0-RS3) ..................................................................................................... 34
The Western Design Center, Inc.
W65C22S Data Sheet
The Western Design Center, Inc. W65C22S Datasheet
4
2.11
RWB (Read/Write) .................................................................................................................. 34
2.12
VDD and VSS. .......................................................................................................................... 34
3. SECTION 3 TIMING, AC AND DC CHARACTERISTICS...................................................... 35
3.1
Absolute Maximum Ratings................................................................................................... 35
3.2
DC Characteristics. TA=-40
C to
+85C
.............................................................................. 36
3.3
AC Characteristic TA=-40
C to
+85
C ............................................................................... 37
3.4
Timing Diagrams...................................................................................................................... 39
4. SECTION 4 CAVEATS ................................................................................................................ 44
4.1
Caveats .................................................................................................................................... 44
5. SECTION 5 HARD CORE MODEL............................................................................................ 45
Application Notes ................................................................................................................................ 45
6. SECTION 6 ORDERING INFORMATION ............................................................................... 46
The Western Design Center, Inc.
W65C22S Data Sheet
The Western Design Center, Inc. W65C22S Datasheet
5
Table of Figures
FIGURE 1-1 READ HANDSHAKE OPERATION (PA ONLY) ..............................................................................................................11
FIGURE 1-2 WRITE HANDSHAKE (PA AND PB).................................................................................................................................12
FIGURE 1-3 ONE-SHOT MODE (TIMER 1 AND TIMER 2)..................................................................................................................17
FIGURE 1-4 FREE-RUN MODE (TIMER 1) ..............................................................................................................................................18
FIGURE1-5 PULSE COUNTING MODE (TIMER 2) ................................................................................................................................20
FIGURE1-6 SHIFT IN - COUNTER T2 CONTROL..................................................................................................................................22
FIGURE-1-7 SHIFT IN - PHI2 CLOCK CONTROL...................................................................................................................................22
FIGURE 1-8 SHIFT IN - EXTERNAL CB1 CLOCK CONTROL TIMING..............................................................................................23
FIGURE 1-9 SHIFT OUT - FREE RUNNING T2 RATE TIMING...........................................................................................................23
FIGURE 1-10 SHIFT OUT - T2 CONTROL TIMING...............................................................................................................................24
FIGURE 1-11 SHIFT OUT - PHI2 CONTROL TIMING...........................................................................................................................24
FIGURE 1-12 SHIFT OUT - EXTERNAL CB1 CLOCK CONTROL TIMING.......................................................................................25
FIGURE 2-1 PIN PLCC PINOUT.................................................................................................................................................................28
FIGURE 2-2 W65C22S 40 PIN PDIP PINOUT...........................................................................................................................................29
FIGURE 2-3 W65C22S 44 PIN QFP PINOUT............................................................................................................................................30
FIGURE 2-4 PORT A BUFFER (PA0-PA7, CA2) .....................................................................................................................................33
FIGURE 2-5 PORT B BUFFER (PB0-PB7, CB1, AND CB2) ....................................................................................................................33
FIGURE 3-1 IDD VS VDD............................................................................................................................................................................36
FIGURE 3-2 F MAX VS VDD......................................................................................................................................................................36
FIGURE 3-3 READ TIMING........................................................................................................................................................................39
FIGURE 4-1 IRQB DIFFERENCE................................................................................................................................................................44
FIGURE 4-2 HIGH RESISTANCE BUS HOLDING DEVICE...................................................................................................................45
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