The Western Design Center, Inc.
September 2003 W65C816 Data Sheet
The Western Design Center, Inc., 2003. All rights reserved
WDC
W65C816S
Microprocessor
DATA SHEET
The Western Design Center, Inc.
W65C816 Data Sheet
The Western Design Center W65C816S
2
WDC reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product. Information contained herein is provided gratuitously and without
liability, to any user. Reasonable efforts have been made to verify accuracy of the information but no
guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every
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application. WDC products are not authorized for use as critical components in life support devices or
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violation of existing patents or other rights of third parties. The sale of any WDC product is subject to
all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon
request.
Copyright (C) 1981-2003 by The
Western Design Center, Inc. All rights reserved, including the right
of reproduction in whole or in part in any form.
The Western Design Center, Inc.
W65C816 Data Sheet
The Western Design Center
W65C816S
3
TABLE OF CONTENTS
1
INTRODUCTION ......................................................................................................................
7
2
W65C816S FUNCTIONAL DESCRIPTION............................................................................
8
2.1
Instruction Register (IR)..........................................................................................................
8
2.2
Timing Control Unit (TCU)......................................................................................................
8
2.3
Arithmetic and Logic Unit (ALU).............................................................................................
8
2.4
Internal Registers (Refer to Programming Model Table 2-2) ...................................................
8
2.5
Accumulator (A).......................................................................................................................
8
2.6
Data Bank Register (DBR).......................................................................................................
9
2.7
Direct (D) .................................................................................................................................
9
2.8
Index (X and Y) ........................................................................................................................
9
2.9
Processor Status Register (P)....................................................................................................
9
2.10
Program Bank Register (PBR).................................................................................................
9
2.11
Program Counter (PC)...........................................................................................................
10
2.12
Stack Pointer (S) ....................................................................................................................
10
3
PIN FUNCTION DESCRIPTION ..........................................................................................
13
3.1
Abort (ABORTB)...................................................................................................................
16
3.2
Address Bus (A0-A15)............................................................................................................
16
3.3
Bus Enable (BE).....................................................................................................................
16
3.4
Data/Bank Address Bus (D0-D7)............................................................................................
17
3.5
Emulation Status (E)..............................................................................................................
17
3.6
Interrupt Request (IRQB)......................................................................................................
17
3.7
Memory Lock (MLB).............................................................................................................
17
3.8
Memory/Index Select Status (MX) .........................................................................................
17
3.9
Non-Maskable Interrupt (NMIB)...........................................................................................
18
3.10
Phase 2 In (PHI2)...................................................................................................................
18
3.11
Read/Write (RWB).................................................................................................................
18
3.12
Ready (RDY)..........................................................................................................................
18
3.13
Reset (RESB)..........................................................................................................................
19
3.14
Valid Data Address (VDA) and Valid Program Address (VPA).............................................
19
3.15
VDD and VSS.........................................................................................................................
19
3.16
Vector Pull (VPB)...................................................................................................................
19
4
ADDRESSING MODES ..........................................................................................................
20
4.1
Reset and Interrupt Vectors ...................................................................................................
20
4.2
Stack ......................................................................................................................................
20
4.3
Direct .....................................................................................................................................
20
4.4
Program Address Space .........................................................................................................
20
4.5
Data Address Space................................................................................................................
20
4.5.1
Absolute -a .................................................................................................................................................................
21
4.5.2
Absolute Indexed Indirect-(a,x) ..........................................................................................................................
21
4.5.3
Absolute Indexed with X-a,x ................................................................................................................................
21
4.5.4
Absolute Indexed with Y-a,y ................................................................................................................................
21
4.5.5
Absolute Indirect-(a)..............................................................................................................................................
22
4.5.6
Absolute Long Indexed With X-al,x ..................................................................................................................
22
4.5.7
Absolute Long-al .....................................................................................................................................................
22
The Western Design Center, Inc.
W65C816 Data Sheet
The Western Design Center W65C816S
4
4.5.8
Accumulator-A ........................................................................................................................................................ 22
4.5.9
Block Move-xyc ....................................................................................................................................................... 22
4.5.10
Direct Indexed Indirect-(d,x).......................................................................................................................... 23
4.5.11
Direct Indexed with X-d,x ............................................................................................................................... 23
4.5.12
Direct Indexed with Y-d,y ............................................................................................................................... 23
4.5.13
Direct Indirect Indexed-(d),y.......................................................................................................................... 24
4.5.14
Direct Indirect Long Indexed-[d],y............................................................................................................... 24
4.5.15
Direct Indirect Long-[d] .................................................................................................................................. 24
4.5.16
Direct Indirect-(d) ............................................................................................................................................. 25
4.5.17
Direct-d................................................................................................................................................................. 25
4.5.18
Immediate-# ........................................................................................................................................................ 25
4.5.19
Implied-i ............................................................................................................................................................... 25
4.5.20
Program Counter Relative Long-rl .............................................................................................................. 25
4.5.21
Program Counter Relative -r........................................................................................................................... 26
4.5.22
Stack-s................................................................................................................................................................... 26
4.5.23
Stack Relative -d,s............................................................................................................................................... 26
4.5.24
Stack Relative Indirect Indexed-(d,s),y ....................................................................................................... 26
5
TIMING, AC AND DC CHARACTERISTICS....................................................................... 28
5.1
Absolute Maximum Ratings ................................................................................................... 28
5.2
DC Characteristics TA = -40
C to +85
C.............................................................................. 29
6
OPERATION TABLES............................................................................................................ 32
7
RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS.............................. 52
7.1
Directives ............................................................................................................................... 52
7.2
Comments .............................................................................................................................. 52
7.3
The Source Line ..................................................................................................................... 52
7.3.1
The Label Field........................................................................................................................................................ 52
7.3.2
The Operation Code Field.................................................................................................................................... 52
7.3.3
The Operand Field.................................................................................................................................................. 53
7.3.4
Comment Field........................................................................................................................................................ 55
8
Caveats...................................................................................................................................... 56
8.1
Stack Addressing .................................................................................................................... 57
8.2
Direct Addressing................................................................................................................... 57
8.3
Absolute Indexed Addressing ................................................................................................. 57
8.4
ABORTB Input...................................................................................................................... 57
8.5
VDA and VPA Valid Memory Address Output Signals .......................................................... 57
8.6
DB/BA operation when RDY is Pulled Low............................................................................ 58
8.7
MX Output............................................................................................................................. 58
8.8
All OpCodes Function in All Modes of Operation.................................................................. 58
8.9
Indirect Jumps ....................................................................................................................... 58
8.10
Switching Modes .................................................................................................................... 58
8.11
How Interrupts Affect the Program Bank and the Data Bank Registers ................................ 58
8.12
Binary Mode .......................................................................................................................... 59
8.13
WAI Instruction..................................................................................................................... 59
8.14
The STP Instruction............................................................................................................... 59
8.15
COP Signatures...................................................................................................................... 59
8.16
WDM OpCode Use................................................................................................................. 59
8.17
RDY Pulled During Write ...................................................................................................... 59
8.18
MVN and MVP Affects on the Data Bank Register................................................................ 59
8.19
Interrupt Priorities................................................................................................................. 60
The Western Design Center, Inc.
W65C816 Data Sheet
The Western Design Center W65C816S
5
8.20
Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers .................................................... 60
8.21
Stack Transfers ...................................................................................................................... 60
8.22
BRK Instruction..................................................................................................................... 60
8.23
Accumulator switching from 8 bit to 16 bit ............................................................................ 60
9
W65C816DB Developer Board and W65C816ICE In-Circuit Emulator (ICE) Board......... 61
9.1
Features: ................................................................................................................................ 61
9.2
Memory map:......................................................................................................................... 61
10
HARD CORE MODEL ........................................................................................................ 62
W65C816 Core Information................................................................................................... 62
10.1
62
11
SOFT CORE RTL MODEL................................................................................................. 63
11.1
W65C816 Synthesizable RTL-Code in Verilog HDL.............................................................. 63
12
ORDERING INFORMATION ............................................................................................ 64
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