7PxxxATA20xxC25
June 2000 Rev. 5 ECO #12935
1
White Electronic Designs Corporation
(508) 366-5151
TECHNICAL SPECIFICATIONS
ATA 20 SERIES FLASH CARDS
7P008ATA2003C25 8MB
7P016ATA2003C25 16MB
7P032ATA2003C25 32MB
7P048ATA2003C25 48MB
7P064ATA2003C25 64MB
7P080ATA2003C25 80MB
7P096ATA2003C25 96MB
7P112ATA2003C25 112MB
7P128ATA2003C25 128MB
7P160ATA2003C25 160MB
Description
Models 7P008ATA20, 7P016ATA20, 7P032ATA20, 7P048ATA20, 7P064ATA20, 7P080ATA20,
7P096ATA20, 7P112ATA20, 7P128ATA20 and 7P160ATA20 are Flash ATA cards. They comply with
the PC card ATA standard and are suitable for usage as a data storage memory medium for PCs or other
electronic equipment. These cards are built with Hitachi 64 Mb Flash memory devices HN29W6411. The
cards are suitable for the ISA (Industry Standard Architecture) bus interface standard. The read/write unit is
1 sector (512 bytes) sequential access.
Features
PC card ATA standard specification
68 pin two piece connector and type I (3.3 mm) or type II (5 mm) stainless steel housing
3.3 V/5 V single power supply operation
ISA standard and Read/Write unit is 512 bytes (sector) sequential access
Sector Read/Write transfer rate: 8MB/sec burst
High reliability based on internal ECC (Error Correcting Code) function
Maximum card density is 160MB
Cards are built with Hitachi 64 Mb Flash memory devices (HN29W6411A)
3 variations of mode access
Memory card mode
I/O card mode
True-IDE mode
Internal self-diagnostic program operates at V
CC
power on
High reliability based on wear leveling function
Data write endurance is 300,000 cycles (with approximately 500 kB DOS file)
Data reliability is 1 error in 10
14
bits read.
Industrial temperature range version: -40
C to +85
C
Auto Sleep Function
7PxxxATA20xxC25
June 2000 Rev. 5 ECO #12935
2
White Electronic Designs Corporation
(508) 366-5151
Card Line Up
Card type
Card
density
Capacity
(3)
Total sectors/
card
(2)
Sectors
/ track
Number of
heads
Number of
cylinder
7P008ATA2003C25
8MB
8,060,928 Byte
15,744
32
2
246
7P016ATA2003C25
16MB
16,121,856 Byte
31,488
32
4
246
7P032ATA2003C25
32MB
32,243,712 Byte
62,976
32
4
492
7P048ATA2003C25
48MB
48,365,568 Byte
94,464
32
4
738
7P064ATA2003C25
64MB
64,487,424 Byte
125,952
32
4
984
7P080ATA2003C25
80MB
80,609,280 Byte
157,440
32
8
615
7P096ATA2003C25
96MB
96,731,136 Byte
188,928
32
8
738
7P112ATA2003C25 112MB
112,852,992 Byte
220,416
32
8
861
7P128ATA2003C25 128MB
128,974,848 Byte
251,904
32
8
984
7P160ATA2003C25 160MB
161,218,560 Byte
314,880
32
16
615
Notes: 1. Total tracks = number of head
number of cylinder.
2. Total sectors/card = sectors/track
number of head
number of cylinder.
3. It is the logical address capacity including the area which is used for file system.
7PxxxATA20xxC25
June 2000 Rev. 5 ECO #12935
5
White Electronic Designs Corporation
(508) 366-5151
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB
and A0 is LSB. In True IDE Mode only HA [2 : 0] are used for selecting the one of eight registers in the
Task File, the remaining address lines should be grounded.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the
Word. D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are
controlled by -CE1 and odd addresses are by -CE2. In True IDE Mode -CE2 is used for select the
Alternate Status Register and the Device Control Register while -CE1 is the chip select for the other task
file registers.
Output enable, ATA select (-OE, -ASTEL: input): -OE is used for the control of data read in Attribute
area or Common memory area. To enable True IDE Mode this input should be grounded by the host.
Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or
Common memory area. In True IDE Mode this input signal is not used and should be connected to VCC.
I/O read (-IORD: input): -IORD is used for control of read data in the Task File area. This card does
not respond to -IORD until I/O card interface setting up.
I/O write (-IOWR: input): -IOWR is used for control of data write in the Task File area. This card does
not respond to -IOWR until I/O card interface setting up.
Ready/Busy, Interrupt request (RDY/-BSY, -IREQ, INTRQ: output): In the I/O card mode, this signal
is -IREQ pin. The signal of low level indicates that the card is requesting software service to the host, and
high level indicates that the card is not requesting. In memory card mode, the signal is RDY/-BSY pin.
RDY/-BSY pin turns low level during the card internal initialization operation at V
CC
applied or reset
applied, so the next access to the card should be after the signal turns high level. In True IDE Mode signal
is the active high Interrupt Request to the host.
Card detection (-CD1, -CD2: output): -CD1 and -CD2 are the card detection signals. -CD1 and -CD2
are connected to ground in this card, so the host can detect if the card is inserted or not.
Write protect, 16 bit I/O port (WP, -IOIS16: output): In memory card mode, WP is held low because
this card does not have a write protect switch. In the I/O card mode, -IOIS16 is asserted when Task File
registers are accessed in 16-bit mode. In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
Attribute memory area selection (-REG: input): -REG should be high level during common memory
area accessing, and low level during Attribute area accessing. The attribute memory area is located only in
an even address, so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses
are invalid in the byte access mode. In True IDE Mode this input signal is not used and should be
connected to VCC.
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