EDI2CG272128V
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst
SRAM, 72 position DIMM (144 contacts) Module, small outline.
The Module contains four (4) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm TQFP
placed on a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sync Burst, Flow-Through, with support for
either linear or sequential burst. This module provides High
Performance, 2-1-1-1 accesses when used in Burst Mode, and
used as a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device architectures.
Synchronous Only operations are performed via strapping ADSC
Low, and ADSP / ADV High, which provides for Ultra Fast Accesses
in Read Mode while providing for internally self-timed Early
Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined for Quad Word access in
both read and write operations.
FEATURES
s 2x128Kx72 Synchronous, Synchronous Burst
s Flow-Through Architecture
s Linear and Sequential Burst Support via MODE pin
s Access Speed(s): T
KHQV
= 8.5, 9, 12, 15ns
s Clock Controlled Registered Bank Enables (E
1
, E
2
)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW)
s Aysnchronous Output Enable (G)
s Internally Self-timed Write
s Individual Bank Sleep Mode Enables (ZZ
1
, ZZ
2
)
s Gold Lead Finish
s 3.3V
10% Operation
s Common Data I/O
s High Capacitance (30pF) Drive, at Rated Access Speed
s Single Total Array Clock
s Multiple Vcc and Gnd
2x128Kx72, 3.3V Sync/Sync Burst Flow-Through
EDI2CG272128V
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
FIG. 1
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DQ
0-63
Input/Output Bus
DQP
0-7
Parity Bits
A
0-16
Address Bus
E
1
, E
2
Synchronous Bank Enables
CLK
Array Clock
GW
Synchronous Global Write
Enable
G
Asynchronous Output Enable
ZZ
1
, ZZ
2
Blank Sleep Mode Enables
Vcc
3.3V Power Supply
Vss
Ground
NC
No Connect
PIN NAMES
PIN
PIN
PIN
PIN
FUNCTION
FUNCTION
FUNCTION
FUNCTION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
V
SS
V
SS
A
0
RFU
A
16
A
1
A
2
A
15
A
14
A
3
A
4
A
13
A
12
A
5
A
6
A
10
A
8
V
CC
G
GW
ADSP
MODE
V
SS
E
1
V
CC
DQ
0
DQ
1
DQ
2
DQ
3
V
SS
ZZ
1
V
CC
DQ
8
DQ
9
DQ
10
DQ
11
V
SS
E
2
V
CC
DQ
16
DQ
17
DQ
18
DQ
19
V
SS
ZZ
2
V
CC
DQ
24
DQ
25
DQ
26
DQ
27
V
SS
RFU
V
CC
DQ
32
DQ
33
DQ
34
DQ
35
V
SS
RFU
V
CC
DQ
40
DQ
41
DQ
42
DQ
43
V
SS
RFU
V
CC
DQ
48
DQ
49
DQ
50
DQ
51
V
SS
RFU
V
CC
DQ
56
DQ
57
DQ
58
DQ
59
V
SS
V
SS
DQ
60
DQ
61
DQ
62
DQ
63
V
CC
DQP
7
V
SS
DQ
52
DQ
53
DQ
54
DQ
55
V
CC
DQP
6
V
SS
DQ
44
DQ
45
DQ
46
DQ
47
V
CC
DQP
5
V
SS
DQ
36
DQ
37
DQ
38
DQ
39
V
CC
DQP
4
V
SS
DQ
28
DQ
29
DQ
30
DQ
31
V
CC
DQP
3
V
SS
DQ
20
DQ
21
DQ
22
DQ
23
V
CC
DQP
2
V
SS
DQ
12
DQ
13
DQ
14
DQ
15
V
CC
DQP
1
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
V
CC
DQP
0
V
SS
CLK
ADSC
ADV
RFU
V
CC
A
9
A
7
A
11
1
2
3
4
5
6
7
8
9
ADSC
ADSP
ADV
CLK
G
GW
A
0-16
ADSC
ADSP
ADV
CLK
G
GW
DQ
E
ZZ
E
1
ZZ
1
ADSC
ADSP
ADV
CLK
G
GW
DQ
E
ZZ
ADSC
ADSP
ADV
CLK
G
GW
DQ
E
ZZ
ADSC
ADSP
ADV
CLK
G
GW
DQ
E
ZZ
U1
U2
U3
U4
E
2
ZZ
2
DQ
0-31
DQP
0-3
DQ
32-63
DQP
4-7
DQ
32-63
DQP
4-7
DQ
0-31
DQP
0-3
PIN SYMBOLS
EDI2CG272128V
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 10, 11, 14, 15,
A
0-16
Input
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
18, 19, 20, 17, 16,
Synchronous
The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
13, 12, 9, 8, 3, 5
25
GW
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE and BWx lines
Synchronous
and must meet the setup and hold times around the rising edge of CLK.
30
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge.
Synchronous
All synchronous inputs must meet setup and hold times around the clock's rising edge.
33, 61
E
1
, E
2
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP
Synchronous
23
G
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
26
ADV
Input
Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin
Synchronous
generates wait cycle (no address advance).
27
ADSP
Input
Address Status Processor: This active LOW input, along with EL and EH being LOW, causes a new externaladdress
Synchronous
to be registered and a READ cycle is initiated using the new address.
28
ADSC
Input
Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external
Synchronous
address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
29
MODE
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST.
47, 75
ZZ
1
, ZZ
2
Input
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode. For normal
Asynchronous
operation, this input has to be either LOW or NC (no connect).
Various
DQ
0-63
Input/Output
Data Inputs/Outputs: First byte is DQ
0-7
, second byte is DQ
8-15
, third byte is DQ
16-23
, fourth byte is DQ
24-31
, fifth byte is
DQ
32-39
, sixth byte is DQ
40-47
, seventh byte is DQ
48-55
and the eight byte is DQ
56-64
.
34, 48, 62, 76,
DQP
0-7
Input/Output
Parity Inputs/Outputs: DQP
0
is parity bit for DQ
0-7
. DQP
1
is parity bit for DQ
8-15
. DQP
2
is parity bit for DQ
16-23
. DQP
3
is
90, 104, 118, 132
parity bit for DQ
24-31
. DQP
4
is parity bit for DQ
32-39
. DQP
5
is parity bit for DQ
40-47
. DQP
6
is parity bit for DQ
48-55
. DQP
7
is parity bit for DQ
56-64
and DQP
7
. In order to use the device configured as a 128K x 64, the parity bits need to be tied to
Vss through a 10K ohm resistor.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
EDI2CG272128V
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1
E2
ADSP
ADSC
ADV
GW
G
CLK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
X
H
H
L
X
L-H
D
Current
EDI2CG272128V
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in operational sections of this
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Voltage on Vcc Relative to Vss
-0.5V to +4.6V
Vin
-0.5V to Vcc +0.5V
Storage Temperature
-55
C to +125
C
Operating Temperature (Commercial)
0
C to +70
C
Operating Temperature (Industrial)
-40
C to +85
C
Short Circuit Output Current
10 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
3.14
3.3
3.6
V
Supply Voltage
V
SS
0.0
0.0
0.0
V
Input High
V
IH
2.0
3.0
V
CC
+0.3
V
Input Low
V
IL
-0.3
0.0
0.8
V
Input Leakage
IL
I
-2
1
2
A
Output Leakage
ILo
-2
1
2
A
Max
Description
Symbol
Typ
8.5
9
12
15
Units
Power Supply Current
Icc
1
1.55
2.2
2.1
2.1
2.0
A
Power Supply Current
Icc
750
1.5
1.5
1.0
1.0
A
Device Selected, No Operation
Snooze Mode
Icc
ZZ
150
200
200
200
200
mA
CMOS Standby
Icc3
400
600
600
600
600
mA
Clock Running-Deselect
IccK
600
1.0
1.0
0.75
0.75
A
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1
E2
GW
G
ZZ
CLK
DQ
Synchronous Write-Bank 1
L
H
L
H
L
High-Z
Synchronous Read-Bank 1
L
H
H
L
L
Synchronous Write-Bank 2
H
L
L
H
L
High-Z
Synchronous Read-Bank 2
H
L
H
L
L
Synchronous Write-Bank 3
H
H
L
H
L
High-Z
Synchronous Read-Bank 3
H
H
H
L
L
Synchronous Write-Bank 4
H
H
L
H
L
High-Z
Synchronous Read-Bank 4
H
H
H
L
L
Snooze Mode
X
X
X
X
H
X
High-Z
AC TEST CIRCUIT
AC TEST CONDITIONS
50
Vt = 1.5V
I/O
Z0 = 50
Z0 = 50
Parameter
I/O
Unit
Input Pulse Levels
V
SS
to 3.0
V
Input and Output Timing Levels
1.25
V
Output Test Equivalencies
See figure, at left
FIG. 2
AC OUTPUT LOAD EQUIVALENT
1.25V
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