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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY*

ARCHITECHTURE

FEATURES

5.0 Volt ± 10% fi r read and write operations

· Minimizes system level power requirements

Compatible with JEDEC-standards

· Pinout and software compatible with single-power

supply Flash

· Superior inadvertent write protection

80 SIMM (JEDEC)

Minimum 100,000 write/erase cycles guaranteed

High

performance

· 70 ns maximum access time

Sector erase architecture

· Uniform sectors of 64 Kbytes each

· Any combination of sectors can be erased. Also

supports full chip erase

Group sector protection

· Hardware method that disables any combination

of sector groups from write or erase operations
(a sector group consists of 4 adjacent sectors of
64Kbytes each)

Embedded

Erase

Algorithms

· Automatically pre-programs and erases the chip

or any sector

Embedded

Program

Algorithms

· Automatically programs and verifi es data at

specifi ed address

Data# Polling and Toggle Bit feature for detection
of program or erase cycle completion

Ready/Busy# output (RY/BY#)

· Hardware method for detection of program or

erase cycle completion

Erase

Suspend/Resume

· Supports reading or programming data to a

sector not being erased

Low power consumption (EDI7292MC)

· 50 mA typical active read current

· 60 mA typical program/erase current

Low power consumption (EDI7492MC)

4MB/8MB (2x2Mx8 / 4x2Mx8) Flash Module 5.0V, Boot-Only
Sector Erase Flash Memory

· 100 mA typical active read current

· 120 mA typical program/erase current

Enhanced power management for standby mode

· <1 µA typical standby current

· Standard access time from standby mode

Hardware RESET# pin

· Resets internal state machine to the read mode

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

DESCRIPTION

The EDI7F292/492MC is a 32/64 Mbit, 5.0 Volt-only
Flash memory organized as 2 Megabytes of 8 bits each.
The 2Mbytes of data is divided into 32 sectors of 64
Kbytes for fl exible erase capability. The 8 bits of data
appear on DQ0DQ7. The EDI7F292/492MC is offered
in 80 Pin SIMM packages. This device is designed to be
programmed in-system with the standard system 5.0 Volt
V

supply. 12.0 Volt V

is not required for program or

erase operations. The device can also be reprogrammed
in standard EPROM programmers.

The standard EDI7F292/492MC offers access times of 100
ns, and 120 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention,
the device has separate chip enable 4 CS#, write enable
WE#, and output enable OE# controls.

The EDI7F292/492MC is entirely command set compatible
with the JEDEC single-power supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from 12.0 Volt Flash or
EPROM devices.

The EDI7F292/492MC is programmed by executing
the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal
algorithm that automatically times the program pulse widths
and verifi es proper cell margin. Erase is accomplished by

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

executing the erase command sequence. This will invoke
the Embedded Erase Algorithm which is an internal
algorithm that automatically preprograms the array if it
is not already programmed before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifi es proper cell margin.

This device also features a sector erase architecture.
This allows for sectors of memory to be erased and
reprogrammed without affecting the data contents of
other sectors. A sector is typically erased and verifi ed
within one second. The EDI7F292/492MC is erased when
shipped .

The EDI7F292/492MC device also features hardware
sector group protection. This feature will disable both
program and erase operations in any combination of
eight sector groups of memory. A sector group consists
of four adjacent sectors grouped in the following pattern:
sectors 03, 47, 811, 1215, 1619, 2023, 2427,
and 2831.

WEDC has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from, or program data to, a sector that
was not being erased. Thus, true background erase can
be achieved.

The device features single 5.0 Volt power supply operation
for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations. A low V

detector automatically inhibits write

operations during power transitions. The end of program
or erase is detected by the RY/BY# pin, Data# polling
of DQ7, or by the Toggle Bit I (DQ6). Once the end of a
program or erase cycle has been completed, the device
automatically resets to the read mode.

The EDI7F292/492MC also has a hardware RESET# pin.
When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm will be
terminated. The internal state machine will then be reset
into the read mode. The RESET# pin may be tied to the
system reset circuitry. Therefore, if a system reset occurs
during the Embedded Program Algorithm or Embedded
Erase Algorithm, the device will be automatically
reset to the read mode. This will enable the system's
microprocessor to read the boot-up fi rmware from the
Flash memory.

The EDI7F292/492MC memory electrically erases all
bits within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a time

using the EPROM programming mechanism of hot electron
injection.

FLEXIBLE SECTOR-ERASE

Thirty two 64 Kbyte sectors

Eight sector groups each of which consists of 4
adjacent sectors in the following pattern: sectors 0-
3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31.

Individual-sector or multiple-sector erase capability

Sector group protection is user-defi nable

SA31
SA30
SA29
SA28

SA3
SA2
SA1
SA0

1FFFFFh
1EFFFFh

1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh

19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
1FFFFFh

1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh

09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh

000000h

Sector

Group

Sector

Group

64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte

32 Sectors Total

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part No.

Symbol

Ordering Park No.

= 5.0 Volt ± 5%

= 5.0 Volt ± 10%

-100

-120

Max Access Time (ns)

100

120

CS# Access (ns)

100

120

OE# Access (ns)

Block Diagrams

EDI7F292MC-BNC: 2x2Mx8 80 PIN SIMM

FIG. 1

EDI7F492MC-BNC: 4x2Mx8 80 PIN SIMM

A0-A20

OE#

RESET#

WE#

2Mx8

DQ0-DQ7

A0-A20

OE#

RESET#

WE#

2Mx8

DQ0-D

PIN CONFIGURATIONS

Pin

Name

Pin

Name

Pin

Name

Pin

Name

CS#

A11

CS#

A10

CS#

DQ7

OE#

CS#

DQ6

WE#

DQ5

461

DQ4

RESET#

DQ3

DQ2

DQ1

DQ0

A20

A19

PD1/NC

A18

PD2/NC

A17

PD3/NC

A16

PD4/NC

A15

PD5/NC

A14

PD6/NC

A13

PD7/NC

A12

Note: Pins 21 and 22 are not connected for EDI7F292MC.

A0-A20

Address input

- CS

Chip Enable

WE#

Write Enable

OE#

Output Enable

DQ0-DQ7

Data Input/Output

PD1-PD7/NC*

Presence Detect

Reset Pin

Power 5V±10%

Ground

No Connect

*Contact factors if PD pin's are needed.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

TABLE 1. EDI7F292/492MC USER BUS OPERATIONS

Module Organization

CS#

OE#

WE#

DQ0-DQ7

RESET#

Autoselect, WEDC Manuf. Code
(1)

Code

Autoselect Device Code (1)

Code

Read

OUT

Standby

HIGH Z

Output Disable

HIGH Z

Write

Enable Sector Group Protect (2)

Verify Sector Group Protect (2)

Code

Temporary Sector Group Unprotect

VID

Hardware Reset/Standby

HIGH Z

Legend:
L = logic 0, H = logic 1, X = Don't Care. See DC Characteristics for voltage levels.
Notes:
1.

Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.

Refer to the section on Sector Group Protection.

READ MODE

The EDI7F292/492MC has two control functions which
must be satisfi ed in order to obtain data at the outputs.
CS# is the power control and should be used for device
selection . OE# is the output control and should be used to
gate data to the output pins if the device is selected.

Address access time (t

ACC

) is equal to the delay from stable

addresses to valid output data. The chip enable access
time (t

) is the delay from stable addresses and stable

CS# to valid data at the output pins. The output enable
access time is the delay from the falling edge of OE# to
valid data at the output pins (assuming the addresses have
been stable for at lease t

ACC

-t

time).

STANDBY MODE

There are two ways to implement the standby mode on
the EDI7F292/492MC device, one using both the CS# and
RESET# pins; the other via the RESET# pin only.

When using both pins, a CMOS standby mode is achieved
with CS# and RESET# inputs both held at V

± 0.3V.

Under this condition the current is typically reduced to
less than 1 µA. A TTL standby mode is achieved with CS#
and RESET# pins held at V

. Under this condition the

current is typically reduced to 200 µA. The device can be
read with standard access time (t

) from either of these

stanby modes.

When using the RESET# pin only, a CMOS standby mode
is achieved with RESET# input held at VSS ± 0.3V (CS#
= don't care). Under this condition the current is typically
reduced to less than 1 µA. A TTL standby mode is achieved
with RESET# pin held at V

(CS# = don't care). Under

this condition the current is typically reduced to less than
200 µA. One the RESET# pin is taken high, the device
requires 50 ns of wake up time before outputs are valid
for read access.

In the standby mode the outputs are in the high impedance
state, independent of the OE# input.

OUTPUT DISABLE

With the OE# input at a logic high level (V

), output from

the device is disabled. This will cause the output pins to
be in a high impedance state.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

AUTOSELECT

The autoselect mode allows the reading of a binary code
from the device and will identify its manufacturer and
type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional over the
entire temperature range of the device.

To activate this mode, the programming equipment must
force VID (11.5 V to 12.5 V) on address pin A9. Two
identifi er bytes may then be sequenced from the device
outputs by toggling address A0 from V

to V

All addresses

are don't cares except A0, A1, and A6 (seeTable 2).

The manufacturer and device codes may also be
read via the command register, for instances when
the EDI7F292/492MC is erased or programmed in a
system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 5 (see Autoselect
Command Sequence).

Byte 0 (A0 = V

) ) represents the manufacturer's code

(WEDC = 01h) and byte 1 (A0 = V

) the device identifi er

code for EDI7F292/492MC = ADh. These two bytes are
given in the table below. All identifi ers for manufacturer
and device will exhibit odd parity with DQ7 defi ned as the
parity bit. In order to read the proper device codes when
executing the Autoselect, A1 must be V

(see Table 2).

The autoselect mode also facilitates the determination
of sector group protection in the system. By performing
a read operation at the address location XX02h with the
higher order address bits A18, A19, and A20 set to the
desired sector group address, the device will return 01h
for a protected sector group and 00h for a non-protected
sector group.

TABLE 2. EDI7F292/492MC SECTOR PROTECTION VERIFY AUTOSELECT CODES

Type

A18 to A20

Code

(HEX)

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Manufacture Code-WEDC

01H

EDI7F292/492MC Devis

ADH

Sector Group Protection

Sector Group

Address

01H*

* Outputs 01H at protected sector addresses

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

TABLE 3. SECTOR ADDRESS TABLE

A20

A19

A18

A17

A16

Address Range

SA0

000000h-00FFFFh

SA1

010000h-01FFFFh

SA2

020000h-02FFFFh

SA3

030000h-03FFFFh

SA4

040000h-04FFFFh

SA5

050000h-05FFFFh

SA6

060000h-06FFFFh

SA7

070000h-07FFFFh

SA8

080000h-08FFFFh

SA9

090000h-09FFFFh

SA10

0A10000h-0AFFFFh

SA11

0B0000h-0BFFFFh

SA12

0C0000h-0CFFFFh

SA13

0D0000h-0DFFFFh

SA14

0E0000h-0EFFFFh

SA15

0F0000h-0FFFFFh

SA16

100000h-10FFFFh

SA17

110000h-11FFFFh

SA18

120000h-12FFFFh

SA19

130000h-13FFFFh

SA20

140000h-14FFFFh

SA21

150000h-15FFFFh

SA22

160000h-16FFFFh

SA23

170000h-17FFFFh

SA24

180000h-18FFFFh

SA25

190000h-19FFFFh

SA26

1A0000h-1AFFFFh

SA27

1B0000h-1BFFFFh

SA28

1C0000h-1CFFFFh

SA29

1D0000h-1DFFFFh

SA30

1E0000h-1EFFFFh

SA31

1F0000h-1FFFFFh

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

TABLE 4. SECTOR GROUP ADDRESS

A20

A19

A18

Sectors

SGA0

SA0-SA3

SGA1

SA4-SA7

SGA2

SA8-SA11

SGA3

SA12-SA15

SGA4

SA16-SA19

SGA5

SA20-SA23

SGA6

SA24-SA27

SGA7

SA28-SA31

WRITE

Device erasure and programming are accomplished via
the command register. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device.

The command register itself does not occupy any
addressable memory location. The register is a latch
used to store the commands, along with the address and
data information needed to execute the command. The
command register is written to by bringing WE# to V

, while

CS# is at V

and OE# is at V

. Addresses are latched on

the falling edge of WE# or CS#, whichever happens later;
while data is latched on the rising edge of WE# or CS#,
whichever happens fi rst. Standard microprocessor write
timings are used.

Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specifi c timing parameters.

SECTOR GROUP PROTECTION

The EDI7F292/492MC features hardware sector group
protection. This feature will disable both program and
erase operations in any combination of eight sector groups
of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors 0-3,
4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see
Table 4). The sector group protect feature is enabled
using programming equipment at the user's site. The
device is shipped with all sector groups unprotected. It is
possible to determine if a sector group is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where
the higher order address bits A18, A19, and A20 is the

desired sector group address, will produce a logical "1"
at DQ0 for a protected sector group. See Table 2 for
Autoselect codes.

TEMPORARY SECTOR GROUP
UNPROTECT

This feature allows temporary unprotection of previously
protected sector groups of the EDI7F292/492MC device
in order to change data in-system. The Sector Group
Unprotect mode is activated by setting the RESET# pin to
high voltage (12V). During this mode, formerly protected
sector groups can be programmed or erased by selecting
the sector group addresses. Once the 12 V is taken away
from the RESET# pin, all the previously protected sector
groups will be protected again. Refer to Figures 15 and
16.

COMMAND DEFINITIONS

Device operations are selected by writing specifi c address
and data sequences into the command register. Writing
incorrect address and data values or writing them in
the improper sequence will reset the device to the
read mode. Table 5 defi nes the valid register command
sequences. Note that the Erase Suspend (B0h) and Erase
Resume (30h) commands are valid only while the Sector
Erase operation is in progress. Moreover, both Reset/Read
commands are functionally equivalent, resetting the device
to the read mode.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

TABLE 5. COMMAND DEFINITION

Command Sequence
Read/Reset

Bus Write

Cycles Req'd

First Bus Write

Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus Write

Cycle

Sixth Bus Write

Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset/Read

XXXXH

F0H

2AAAH

Reset/Read

5555H

AAH

2AAAH

55H

5555H

F0H

Autoselect

5555H

AAH

2AAAH

55H

5555H

90H

Byte Program

5555H

AAH

2AAAH

55H

5555H

A0H

Data

Chip Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Sector Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

30H

Erase Suspend

XXXXH

B0H

Erase Suspend

XXXXH

30H

Notes:
1.

Bus operations are defi ned in Table 1.

RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE#
SA= Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select any sector.

RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#

Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.

Address bits A15, A14, A13, A12 and A11 = X, X = don't care.

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until the
command register contents are altered.

The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during
the power transition. Refer to the AC Read Characteristics
and Waveforms for the specifi c timing parameters.

AUTOSELECT COMMAND

Flash memories are intended for use in applications
where the local CPU can alter memory contents. As such,
manufacture and device codes must be such, manufacture
and device codes must be tem. PROM programmers
typically access the signature codes by raising A9 to a
high voltage. However, multiplexing high voltage onto the
address lines is not generally a desirable system design
practice. The device contains an autoselect command

operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the
autoselect command sequence into the command register.
Following the command write, a read cycle from address
XX00h retrieves the manufacturer code of 01h. A read
cycle from address XX01h returns the device code ADh
(see Table 2).

All manufacturer and device codes will exhibit odd parity
with DQ7 defi ned as the parity bit.

Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector group addresses
(A18, A19, and A20) while (A6, A1, A0) = (0, 1, 0) will
produce a logical "1" at device output DQ0 for a protected
sector group.

To terminate the operation, it is necessary to write the
read/reset command sequence into the register.

BYTE PROGRAMMING

The device is programmed on a byte-by-byte basis.
Programming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program
set-up command and data write cycles. Addresses are

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EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

latched on the falling edge of CS# OR WE#, whichever
happens later and the data is latched on the rising edge of
CS# or WE#, whichever happens fi rst. The rising edge of
CS# or WE# (whichever happens fi rst) begins programming
using the Embedded Program Algorithm. Upon executing
the algorithm, the system is not required to provide further
controls or timings. The device will automatically provide
adequate internally generated program pulses and verify
the programmed cell margin.

This automatic programming operation is completed when
the data on DQ7 (also used as Data# Polling) is equivalent
to the data written to this bit at which time the device returns
to the read mode and addresses are no longer latched (see
Table 6, Write Operation Status). Therefore, the device
requires that a valid address to the device be supplied
by the system at this particular instance of time for Data#
Polling operations. Data# Polling must be performed at the
memory location which is being programmed.

Any commands written to the chip during the Embedded
Program Algorithm will be ignored. If a hardware reset
occurs during the programming operation, the data at that
particular location will be corrupted.

Programming is allowed in any sequence and across sector
boundaries. Beware that a data "0" cannot be programmed
back to a "1". Attempting to do so may either hang up the
device or result in an apparent success according to the
data polling algorithm but a read from reset/read mode will
show that the data is still "0". Only erase operations can
convert "0"s to "1"s.

Figure 1 illustrates the Embedded Programming Algorithm
using typical command strings and bus operations.

CHIP ERASE

Chip erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are
then followed by the chip erase command.

Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations.

The automatic erase begins on the rising edge of the last
WE# pulse in the command sequence and terminates
when the data on DQ7 is "1" (see Write Operation Status

section) at which time the device returns to read mode.

Figure 2 illustrates the Embedded Erase Algorithm using
typical command strings and bus operations.

SECTOR ERASE

Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE#, while the command
(30h) is latched on the rising edge of WE#. After a time-
out of 50 µs from the rising edge of the last sector erase
command, the sector erase operation will begin.

Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less
than 50 µs otherwise that command will not be accepted
and erasure will start. It is recommended that processor
interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last
Sector Erase command is written. A time-out of 50 µs from
the rising edge of the last WE# will initiate the execution
of the Sector Erase command(s). If another falling edge
of the WE# occurs within the 50 µs time-out window the
timer is reset. (Monitor DQ3 to determine if the sector
erase timer window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase or
Erase Suspend during this period will reset the device to
the read mode, ignoring the previous command string. In
that case, restart the erase on those sectors and allow
them to complete.(Refer to the Write Operation Status
section for DQ3, Sector Erase Timer, operation.) Loading
the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 31).

Sector erase does not require the user to program the
device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior
to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system
is not required to provide any controls or timings during
these operations.

The automatic sector erase begins after the 50 µs time out
from the rising edge of the WE# pulse for the last sector
erase command pulse and terminates when the data on

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EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

DQ7, Data# Polling, is "1" (see Write Operation Status
section) at which time the device returns to the read mode.
Data# Polling must be performed at an address within any
of the sectors being erased.

Figure 2 illustrates the Embedded Erase Algorithm using
typical command strings and bus operations.

ERASE SUSPEND

The Erase Suspend command allows the user to interrupt
a Sector Erase operation and then perform data reads or
programs to a sector not being erased. This command is
applicable ONLY during the Sector Erase operation which
includes the time-out period for sector erase. The Erase
Suspend command will be ignored if written during the Chip
Erase operation or Embedded Program Algorithm. Writing
the Erase Suspend command during the Sector Erase
time-out results in immediate termination of the time-out
period and suspension of the erase operation.

Any other command written during the Erase Suspend
mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase
operation. The addresses are "don't-cares" when writing
the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the
Sector Erase operation, the device will take a maximum
of 15 µs to suspend the erase operation. When the device
has entered the erase-suspended mode, the RY/BY#
output pin and the DQ7 bit will be at logic `1', and DQ6
will stop toggling. The user must use the address of the
erasing sector for reading DQ6 and DQ7 to determine if

the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device
defaults to the erase-suspend-read mode. Reading data in
this mode is the same as reading from the standard read
mode except that the data must be read from sectors that
have not been erase-suspended. Successively reading
from the erase-suspended sector while the device is in
the erase-suspend-read mode will cause DQ2 to toggle.
(See the section on DQ2).

After entering the erase-suspend-read mode, the user can
program the device by writing the appropriate command
sequence for Byte Program. This program mode is
known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in
the regular Byte Program mode except that the data must
be programmed to sectors that are not erase-suspended.
Successively reading from the erase-suspended sector
while the device is in the erase-suspend-program mode
will cause DQ2 to toggle. The end of the erase-suspended
program operation is detected by the RY/BY# output pin,
Data# Polling of DQ7, or by the Toggle Bit I (DQ6) which
is the same as the regular Byte Program operation. Note
that DQ7 must be read from the byte program address
while DQ6 can be read from any address.

To resume the operation of Sector Erase, the Resume
command (30h) should be written. Any further writes of the
Resume command at this point will be ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

TABLE 6. WRITE OPERATION STATUS

In Progress

Status

DQ7

CQ6

DQ5

DQ3

DQ2

Byte Program in Embedded Program Algorithm

DQ7#

Toggle

Embedded Program Algorithm

Toggle

Erase Suspended Mode

Erase Suspended Read
(Erase Suspended Sector)

Toggle

(Note 1)

Erase Suspended Read
(Non-Erase Suspended Sector)

Data

Erase Suspended Read
(Non-Erase Suspended Sector)

DQ7#

Toggle

(Note 2)

(Note 3)

Exceeded Time

Limits

Byte Program in Embedded Program Algorithm

DQ7#

Toggle

Program/Erase Program in Embedded Program Algorithm

Toggle

N/A

Erase Suspended Mode

Erase Suspended Read
(Non-Erase Suspended Sector)

DQ7#

Toggle

N/A

Notes:
1.

Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.

Performing successive read operations from any address will cause DQ6 to toggle.

Reading the byte address being programmed while in the erase-suspend program mode will indicate logic `1' at the DQ2 bit.
However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

DQ7

DATA# POLLING

The EDI7F292/492MC device features Data# Polling
as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the
Embedded Program Algorithm, an attempt to read the
device will produce the complement of the data last written
to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the
true data last written to DQ7. During the Embedded Erase
Algorithm, an attempt to read the device will produce a
"0" at the DQ7 output. Upon completion of the Embedded
Erase Algorithm an attempt to read the device will produce
a "1" at the DQ7 output. The fl owchart for Data# Polling
(DQ7) is shown in Figure 3.

Data# Polling will also fl ag the entry into Erase Suspend.
DQ7 will switch "0" to "1" at the start of the Erase Suspend
mode. Please note that the address of an erasing sector
must be applied in order to observe DQ7 in the Erase
Suspend Mode.

During Program in Erase Suspend, Data# Polling will
perform the same as in regular program execution outside
of the suspend mode.

For chip erase, the Data# Polling is valid after the
rising edge of the sixth WE# pulse in the six write pulse

sequence. For sector erase, the Data# Polling is valid after
the last rising edge of the sector erase WE# pulse. Data#
Polling must be performed at sector addresses within any
of the sectors being erased and not a sector that is within
a protected sector group. Otherwise, the status may not
be valid.

Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while the
output enable (OE#) is asserted low. This means that the
device is driving status information on DQ7 at one instant
of time and then that byte's valid data at the next instant
of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the
device has completed the Embedded Algorithm operations
and DQ7 has a valid data, the data outputs on DQ0DQ6
may be still invalid. The valid data on DQ0DQ7 can be
read on the successive read attempts.

The Data# Polling feature is only active during the
Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode,
or sector erase time-out (see Table 6).

See Figure 11 for the Data# Polling timing specifi cations
and diagrams.

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EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

DQ6

TOGGLE BIT I

The EDI7F292/492MC also features the "Toggle Bit I" as a
method to indicate to the host system that the embedded
algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle,
successive attempts to read (OE# toggling) data from the
device at any address will result in DQ6 toggling between
one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ6 will stop toggling and
valid data will be read on the next successive attempts.
During programming, the Toggle Bit I is valid after the
rising edge of the fourth WE# pulse in the four write pulse
sequence. For chip erase, the Toggle Bit I is valid after the
rising edge of the sixth WE# pulse in the six write pulse
sequence. For Sector Erase, the Toggle Bit I is valid after
the last rising edge of the sector erase WE# pulse. The
Toggle Bit I is active during the sector erase time out.

Either CS# or OE# toggling will cause the DQ6 to toggle.
In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 12 for the Toggle Bit I
timing specifi cations and diagrams.

DQ5

EXCEEDED TIMING LIMITS

DQ5 will indicate if the program or erase time has
exceeded the specifi ed limits (internal pulse count). Under
these conditions DQ5 will produce a "1". This is a failure
condition which indicates that the program or erase cycle
was not successfully completed. Data# Polling is the only
operating function of the device under this condition. The
CS# circuit will partially power down the device under these
conditions (to approximately 2 mA). The OE# and WE#
pins will control the output disable functions as described
in Table 1.

The DQ5 failure condition will also appear if a user tries to
program a "1" to a location that is previously programmed
to "0". In this case the device locks out and never
completes the Embedded Program Algorithm. Hence, the
system never reads a valid data on DQ7 bit and DQ6 never
stops toggling. Once the device has exceeded timing limits,
the DQ5 bit will indicate a "1." Please note that this is not
a device failure condition since the device was incorrectly
used. If this occurs, reset the device.

DQ3

SECTOR ERASE TIMER

After the completion of the initial sector erase command
sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit I are valid after the initial sector erase
command sequence. If Data# Polling or the Toggle Bit I
indicates the device has been written with a valid erase
command, DQ3 may be used to determine if the sector
erase timer window is still open. If DQ3 is high ("1") the
internally controlled erase cycle has begun; attempts to
write subsequent commands (other than Erase Suspend)
to the device will be ignored until the erase operation is
completed as indicated by Data# Polling or Toggle Bit I. If
DQ3 is low ("0"), the device will accept additional sector
erase commands. To insure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 were high on the second status check,
the command may not have been accepted.

Refer to Table 6: Write Operation Status.

DQ2

TOGGLE BIT II

This toggle bit, along with DQ6, can be used to determine
whether the device is in the Embedded Erase Algorithm
or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive
reads from the erase-suspend sector will cause DQ2
to toggle. When the device is in the erase-suspended-
program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic `1'
at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only
when the standard Program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these
two status bits, along with that of DQ7, is summarized as
follows:

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

Mode

DQ7

DQ6

DQ2

Program

DQ7#

toggles

Erase

toggles

Erase Suspend Read (1)

(Erase-Suspend Sector)

toggles

Erase Suspend Program

DQ7# (2)

toggles

1 (2)

Notes:
1.

These status fl ags apply when outputs are read from a sector that has been
erase-suspended.

These status fl ags apply when outputs are read from the byte address of the
non-erase suspended sector.

For example, DQ2 and DQ6 can be used together to
determine the erase-suspend-read mode (DQ2 toggles
while DQ6 does not). See also Table 6 and Figure 17.
Furthermore, DQ2 can also be used to determine which
sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing
sector.

RY/BY#

READY/BUSY#

The EDI7F292/492MC provides a RY/BY# open-drain
output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has
been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is
high, the device is ready to accept any read/write or erase
operation. When the RY/BY# pin is low, the device will
not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the
EDI7F292/492MC is placed in an Erase Suspend mode,
the RY/BY# output will be high.

During programming, the RY/BY# pin is driven low after
the rising edge of the fourth WE# pulse. During an erase
operation, the RY/BY# pin is driven low after the rising
edge of the sixth WE# pulse. The RY/BY# pin will indicate
a busy condition during the RESET# pulse. Refer to Figure
13 for a detailed timing diagram. The RY/BY# pin is pulled
high in standby mode.

Since this is an open-drain output, several RY/BY# pins
can be tied together in parallel with a pull-up resistor to
V

RESET#

HARDWARE RESET

The EDI7F292/492MC device may be reset by driving the
RESET# pin to V

. The RESET# pin must be kept low

) for at least 500 ns. Any operation in progress will be

terminated and the internal state machine will be reset to
the read mode 20 µs after the RESET# pin is driven low.
If a hardware reset occurs during a program operation, the
data at that particular location will be indeterminate.

When the RESET# pin is low and the internal reset is
complete, the device goes to standby mode and cannot
be accessed. Also, note that all the data output pins are
tri-stated for the duration of the RESET# pulse. Once
the RESET# pin is taken high, the device requires
500 ns of wake up time until outputs are valid for read
access. The RESET# pin may be tied to the system
reset input. Therefore, if a system reset occurs during the
Embedded Program or Erase Algorithm, the device will
be automatically reset to read mode and this will enable
the system's microprocessor to read the boot-up fi rmware
from the Flash memory.

DATA PROTECTION

The EDI7F292/492MC is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specifi c multi-bus cycle command sequences.

The device also incorporates several features to prevent
inadvertent write cycles resulting from V

power-up and

power-down transitions or system noise.

LOW V

WRITE INHIBIT

To avoid initiation of a write cycle during V

power-up and

power-down, a write cycle is locked out for V

less than

3.2 V (typically 3.7 V). If V

< V

LKO

, the command register

is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the
read mode. Subsequent writes will be ignored until the V

level is greater than V

LKO

. It is the user's responsibility to

ensure that the control pins are logically correct to prevent
unintentional writes when V

is above 3.2 V.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5 ns (typical) on OE#, CS# or
WE# will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = V

, CS#

or WE# = V

. To initiate a write cycle CS# and WE#

must be a logical zero while OE# is a logical one.

POWER-UP WRITE INHIBIT

Power-up of the device with WE# = CS# = V

, and OE#

= V

will not accept command on the rising edge of WE#

The internal state machine is automatically reset to the
read mode on power-up.

FIGURE 1. EMBEDDED PROGRAMMING ALGORITHM

Start

Programming Completed

Last Address

Write Program Command Sequence

(see below)

Data# Poll Device

Increment Address

Yes

5555h/AAh

2AAAh/55h

5555h/A0h

Program Address/Program Data

Program Command Sequence (Address/Command):

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

Storage Temperature
Plastic Packages .................................. 65°C to +150°C

Ambient Temperature
with Power Applied ............................... 65°C to +125°C

Voltage with Respect to Ground

(Note 1) ...................................... 2.0 V to +7.0 V

A9, OE#, and RESET# (Note 2) ...... 2.0 V to +13.5 V

All other pins (Note 1) ........................ 2.0 V to +7.0 V

Output Short Circuit Current (Note 3) ................. 200 mA

ABSOLUTE MAXIMUM RATINGS

Notes:
1.

Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions,
input may overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC

voltage on input or I/O pins is V

+0.5 V. During voltage transitions, input or I/O

pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During
voltage transitions, A9, OE#, and RESET# may overshoot V

to 2.0 V for

periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.

No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Case Temperature (T

) .............................. 0°C to +70°C

Industrial (I) Devices

Case Temperature (T

) .......................... 40°C to +85°C

Supply Voltages

for EDI7F292/492MC ................ +4.75 V to +5.25 V

for EDI7F292/492MC 100, 120 .. +4.50 V to +5.50 V

Operating ranges defi ne those limits between which the functionality of the device is
guaranteed.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

DC CHARACTERISTICS (EDI7F292MC)

TTL/NMOS COMPATIBLE

Parameter
Symbol

Parameter Description

Test Description

Min

Max

Units

Input Load Current

= V

to V

= V

CCMAX

±1.0

µA

LIT

A9 Input Load Current

= V

CCMAX

, A9 = 12.0 Volt

µA

Output Leakage Current

OUT

= V

to V

, V

= V

CCMAX

±1.0

µA

CC1

Active Current (Note 1)

CS# = V

, OE# = V

CC2

Active Current (Notes 2, 3)

CS# = V

, OE# = V

120

CC3

Standby Current

= V

CCMAX

, CS# = V

, RESET# = V

CC4

Standby Current (Reset)

= V

CCMAX

, RESET# = V

Input Low Level

-0.5

0.8

Input High Level

2.0

+ 0.5

Voltage for Autoselect and
Sector Protect

= 5.0 Volt

11.5

12.5

Output Low Voltage

= 12 mA V

= V

CCMIN

0.45

Output High Level

= -2.5 mA V

= V

CCMIN

2.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Notes:
1. The

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,

with OE# at V

2. I

active while Embedded Program or Erase Algorithm is in progress.

3. Not

100%

tested.

DC CHARACTERISTICS (EDI7F292MC)

CMOS COMPATIBLE

Parameter
Symbol

Parameter Description

Test Description

Min

Typ

Max

Units

Input Load Current

= V

to V

, V

= V

CCMAX

±1.0

µA

LIT

A9 Input Load Current

= V

CCMAX

, A9 = 12.0 Volt

µA

Output Leakage Current

OUT

= V

to V

, V

= V

CCMAX

±1.0

µA

CC1

Active Current (Note 1)

CS# = V

, OE# = V

CC2

Active Current (Notes 2, 3)

CS# = V

, OE# = V

CC3

Standby Current

= V

CCMAX

, CS# = V

± 0.3 V, RESET#

= V

± 0.3 V

CC4

Standby Current (Reset)

= V

CCMAX

, RESET# = V

± 0.3 V

Input Low Level

-0.5

0.8

Input High Level

0.7 X V

+ 0.3

Voltage for Autoselect and
Sector Protect

= 5.0 Volt

11.5

12.5

Output Low Voltage

= 12 mA V

= V

CCMIN

0.85 V

0.45

Output High Level

= -2.5 mA V

= V

CCMIN

2.4

= -100 µA, V

= V

CCMIN

- 0.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Notes:
1. The

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,

with OE# at V

2. I

active while Embedded Program or Erase Algorithm is in progress.

3. Not

100%

tested.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

DC CHARACTERISTICS (EDI7F492MC)

TTL/NMOS COMPATIBLE

Parameter
Symbol

Parameter Description

Test Description

Min

Max

Units

Input Load Current

= V

to V

= V

CCMAX

±1.0

µA

LIT

A9 Input Load Current

= V

CCMAX

, A9 = 12.0 Volt

µA

Output Leakage Current

OUT

= V

to V

, V

= V

CCMAX

±1.0

µA

CC1

Active Current (Note 1)

CS# = V

, OE# = V

160

CC2

Active Current (Notes 2, 3)

CS# = V

, OE# = V

240

CC3

Standby Current

= V

CCMAX

, CS# = V

, RESET# = V

CC4

Standby Current (Reset)

= V

CCMAX

, RESET# = V

Input Low Level

-0.5

0.8

Input High Level

2.0

+ 0.5

Voltage for Autoselect and
Sector Protect

= 5.0 Volt

11.5

12.5

Output Low Voltage

= 12 mA V

= V

CCMIN

0.45

Output High Level

= -2.5 mA V

= V

CCMIN

2.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Notes:
1. The

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,

with OE# at V

2. I

active while Embedded Program or Erase Algorithm is in progress.

3. Not

100%

tested.

DC CHARACTERISTICS (EDI7F492MC)

CMOS COMPATIBLE

Parameter
Symbol

Parameter Description

Test Description

Min

Typ

Max

Units

Input Load Current

= V

to V

, V

= V

CCMAX

±1.0

µA

LIT

A9 Input Load Current

= V

CCMAX

, A9 = 12.0 Volt

µA

Output Leakage Current

OUT

= V

to V

, V

= V

CCMAX

±1.0

µA

CC1

Active Current (Note 1)

CS# = V

, OE# = V

100

160

CC2

Active Current (Notes 2, 3)

CS# = V

, OE# = V

120

160

CC3

Standby Current

= V

CCMAX

, CS# = V

± 0.3 V, RESET#

= V

± 0.3 V

CC4

Standby Current (Reset)

= V

CCMAX

, RESET# = V

± 0.3 V

Input Low Level

-0.5

0.8

Input High Level

0.7 X V

+ 0.3

Voltage for Autoselect and
Sector Protect

= 5.0 Volt

11.5

12.5

Output Low Voltage

= 12 mA V

= V

CCMIN

0.85 V

0.45

Output High Level

= -2.5 mA V

= V

CCMIN

2.4

= -100 µA, V

= V

CCMIN

- 0.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Notes:
1. The

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,

with OE# at V

2. I

active while Embedded Program or Erase Algorithm is in progress.

3. Not

100%

tested.

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

AC CHARACTERISTICS

READ-ONLY OPERATIONS CHARACTERISTICS

Parameter Symbol

Parameter Desription

Test Setup

Speed Options (Notes 1 and 2)

JEDEC

Standard

-100

-120

AVAV

Read Cycle Time 4

CS# = V

OE# = V

Min

100

120

AVQV

ACC

Address to Output Delay

OE# = V

Max

100

120

ELQV

Chip Enable to Output Delay

Max

100

120

GLQV

Output Enable to Output Delay

Max

EHQZ

Chip Enable to Output High Z (Notes 3, 4)

Max

GHQZ

Output Enable to Output High Z (Notes 3, 4)

Max

AXQX

Output Hold Time From Addresses CS# or
OE# Which Ever Occurs First

Min

Ready

RESET# Pin Low to Read Mode 4

Max

Notes:
1.

Test Conditions (for all others): Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level: 0.8 V
and 2.0 V input and output.

Output driver disable time.

3. Not

100%

tested.

FIGURE 7 TEST CONDITIONS

2.7 k

Diodes = 1N3064
or Equivalent

6.2 k

5.0 Volt

1N3064

or Equivalent

Device

Under

Test

Note:
CL = 100 pF including jig capacitance

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White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

AC CHARACTERISTICS

WRITE/ERASE/PROGRAM OPERATIONS

Parameter Symbol

Parameter Desription

Speed Options (Notes 1 and 2)

JEDEC

Standard

-100

-120

AVAV

Write Cycle Time

Min

100

120

AVWL

Address Setup Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OEH

Output Enable Hold
Time

Min

Toggle Bit I and
Data# Polling 2

Min

GHWL

Read Recover Time Before Write OE# high to
WE# low

Min

ELWL

CS# Setup Time

Min

WHEH

CS# Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width High

Min

WHWH1

Byte Programming Operation

Typ

WHWH2

Sector Erase Operation 1

Typ

Max

VCS

Set Up Time 2

Min

VIDR

Rise Time to VID (Notes 2, 3)

Min

500

VLHT

Voltage Transition Time (Notes 2, 3)

Min

OESP

OE# Setup Time to WE# Active ( 2, 3)

Min

RESET# Pulse Width

Min

500

BUSY

Program/Erase Valid to RY/BY# Delay

Min

Notes:
1.

This does not include the preprogramming time.

2. Not

100%

tested.

These timings are for Temporary Sector Group Unprotect operation.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

SWITCHING WAVEFORMS

FIGURE 9. PROGRAM OPERATION TIMINGS

OUT

Data# Polling

WPH

GHWL

Addresses

CE#

WE#

Data

5.0 Volt

DQ7

5555H

A0H

WHWH1

3rd Bus Cycle

Notes:
1.

PA is address of the memory location to be programmed.

PD is data to be programmed at byte address.

DQ7# is the output of the complement of the data written to the device.

4. D

OUT

is the output of the data written to the device.

Figure indicates last two bus cycles of four bus cycle sequence.

FIGURE 10. AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS

5555H

2AAAH

CS#

OE#

WE#

Data

AAH

55H

80H

AAH

55H

10H/30H

WPH

Addresses

2AAAH

VCS

5555H

GHWL

5555H

Notes:
1.

SA is the sector address for Sector Erase. Addresses = don't care for Chip Erase.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

AC CHARACTERISTICS

WRITE/ERASE/PROGRAM OPERATIONS

Alternate CS# Controlled Writes

Parameter Symbol

Parameter Desription

Speed Options (Notes 1 and 2)

JEDEC

Standard

-100

-120

AVAV

Write Cycle Time

Min

100

120

AVWL

Address Setup Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OEH

Output Enable Hold
Time

Read (Note 2)

Min

Toggle Bit I and
Data# Polling
(Note 2)

Min

GHWL

Read Recover Time Before Write OE# high to
WE# low

Min

ELWL

CS# Setup Time

Min

WHEH

CS# Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width High

Min

WHWH1

Byte Programming Operation

Typ

WHWH2

Sector Erase Operation (Note 1)

Typ

Max

Notes:
1.

This does not include the preprogramming time.

2. Not

100%

tested.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

FIGURE 18. ALTERNATE CS# CONTROLLED PROMGRAM OPERATION TIMING

OUT

Data# Polling

CPH

GHEL

Addresses

WE#

OE#

CS#

Data

5.0 Volt

DQ7#

5555H

A0H

WHWH1

Notes:
1.

PA is address of the memory location to be programmed.

PD is data to be programmed at byte address.

DQ7# is the output of the complement of the data written to the device.

4. D

OUT

is the output of the data written to the device.

Figure indicates last two bus cycles of four bus cycle sequence.

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Limits

Unit

Comments

Min

Typ

Max

Sector Erase Time

1 (Note 1)

sec

Excludes 00H programming prior to erasure

Chip Erase Time

256

sec

Excludes 00H programming prior to erasure

Byte Programming Time

300 ( Note 3)

µs

Excludes system-level overhead

Chip Programming Time

14.4 (Note 1)

43.2 (Notes 2, 3)

sec

Excludes system-level overhead

Notes:
1.

25°C, 5V V

, 100,000 cycles.

Although Embedded Algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase signifi cantly faster than the
worst case byte.

Under worst case condition of 90°C, 4.5 V V

, 100,000 cycles.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

EDI7F292MC
EDI7F492MC

January 2006
Rev. 1

PRELIMINARY

ORDERING IN FOR MA TION

EDI7292MC

5.72

(0.225)

MIN

3.18

(0.125)

MIN

3.05

(0.120)

MAX

153

1.57

(0.062) R

1.57 (0.062) R

21.59

(0.850)

MAX

118.24

(4.655) MAX.

111.35

(4.384)

6.35

(0.250)

57.02

(2.245)

55.68

(2.192)

10.16

(0.400)

105.41

(4.150)

1.27

(0.050) TYP

6.35 (0.250)

EDI7292MC

Part Num ber

Speed (ns)

Pack age

Commercial Range

Height*

EDI7292MC100BNC

100

361

0°C to +70°C

21.59 (0.850")

EDI7292MC120BNC

120

361

0°C to +70°C

21.59 (0.850")

EDI7492MC

Part Num ber

Speed (ns)

Pack age

Industrial Range

Height*

EDI7492MC100BNI

100

361

0°C to +70°C

21.59 (0.850")

EDI7492MC120BNI

120

361

0°C to +70°C

21.59 (0.850")

Notes:
· Consult factors for availability of lead-free or RoHS products.
· Consult factors for availability of industrail temp (-40°C to 85°C) option.

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

EDI7492MC

5.72

(0.225)

MIN

3.18

(0.125)

MIN

4.32

(0.170)

MAX

153

1.57

(0.062) R

1.57 (0.062) R

21.59

(0.850)

MAX

118.24

(4.655) MAX.

111.35

(4.384)

6.35

(0.250)

57.02

(2.245)

55.68

(2.192)

10.16

(0.400)

105.41

(4.150)

1.27

(0.050) TYP

6.35 (0.250)

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

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