1
White Electronic Designs Corporation www.whiteedc.com (602) 437-1520
HI-RELIABILITY PRODUCT
EDI88512C
512Kx8 Monolithic SRAM CMOS
FEATURES
s 512Kx8 bit CMOS Static
s Random Access Memory
Access Times of 70, 85, 100ns
Data Retention Function (LP version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
s 32 lead JEDEC Approved Evolutionary Pinout
Ceramic Sidebrazed 600 mil DIP (Package 9)
Ceramic SOJ (Package 140)
s Single +5V (
10%) Supply Operation
February 2001 Rev. 11
PIN DESCRIPTION
I/O
0-7
Data Inputs/Outputs
A
0-18
Address Inputs
WE
Write Enables
CS
Chip Selects
OE
Output Enable
V
CC
Power (+5V
10%)
V
SS
Ground
NC
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
-18
I/O
-7
WE
CS
OE
FIG. 1
PIN CONFIGURATION
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. Both the DIP and CSOJ packages are
pin for pin upgrades for the single chip enable 128K x 8, the
EDI88128C. Pins 1 and 30 become the higher order addresses.
A Low Power version with Data Retention (EDI88512LP) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
2
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI88512C
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on any pin relative to Vss
-0.5 to 7.0
V
Operating Temperature T
A
(Ambient)
Commercial
0 to +70
C
Industrial
-40 to +85
C
Military
-55 to +125
C
Storage Temperature, Plastic
-65 to +150
C
Power Dissipation
1
W
Output Current
20
mA
Junction Temperature, T
J
175
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
Vcc +0.5
V
Input Low Voltage
V
IL
-0.3
--
+0.8
V
Parameter
Symbol
Condition
Max Unit
Address Lines
C
I
V
IN
= Vcc or Vss, f = 1.0MHz
12
pF
Data Lines
C
O
V
OUT
= Vcc or Vss, f = 1.0MHz
14
pF
These parameters are sampled, not 100% tested.
CAPACITANCE
(T
A
= +25
C)
TRUTH TABLE
OE
CS
WE
Mode
Output
Power
X
H
X
Standby
High Z
Icc
2
, Icc3
H
L
H
Output Deselect
High Z
Icc
1
L
L
H
Read
Data Out
Icc
1
X
L
L
Write
Data In
Icc
1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
30pF
480
Vcc
Q
Figure 1
Figure 2
255
5pF
480
Vcc
Q
255
AC TEST CONDITIONS
Parameter
Symbol
Conditions
Units
Min
Typ*
Max
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
--
--
10
A
Output Leakage Current
I
LO
V
I/O
= 0V to V
CC
--
--
10
A
Operating Power Supply Current
I
CC1
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle (70-100ns)
--
45
75
mA
Standby (TTL) Power Supply Current
I
CC2
CS
V
IH
, V
IN
V
IL
, V
IN
V
IH
--
3
10
mA
Full Standby Power Supply Current
I
CC3
CS
V
CC
-0.2V
C
--
--
5
mA
V
IN
Vcc -0.2V or V
IN
0.2V
LP
--
--
2
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA
--
--
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0mA
2.4
--
--
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
DC CHARACTERISTICS
(V
CC
= 5V, *T
A
= -55
C to +125
C)
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White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI88512C
AC CHARACTERISTICS READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0
C to +70
C)
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
70
85
100
ns
Address Access Time
t
AVQV
t
AA
70
85
100
ns
Chip Enable Access Time
t
ELQV
t
ACS
70
85
100
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
10
10
10
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
25
30
30
ns
Output Hold from Address Change
t
AVQX
t
OH
10
10
10
ns
Output Enable to Output Valid
t
GLQV
t
OE
35
45
50
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
5
5
5
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
0
25
0
30
0
30
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0
C to +70
C)
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
70
85
100
ns
Chip Enable to End of Write
t
ELWH
t
CW
60
70
80
ns
t
ELEH
t
CW
60
70
80
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
t
AVEL
t
AS
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
65
70
80
ns
t
AVEH
t
AW
65
70
80
ns
Write Pulse Width
t
WLWH
t
WP
50
55
60
ns
t
WLEH
t
WP
50
55
60
ns
Write Recovery Time
t
WHAX
t
WR
0
0
0
ns
t
EHAX
t
WR
0
0
0
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
t
EHDX
t
DH
0
0
0
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
25
0
30
0
30
ns
Data to Write Time
t
DVWH
t
DW
40
40
40
ns
t
DVEH
t
DW
30
35
40
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
5
5
5
ns
1. This parameter is guaranteed by design but not tested.
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White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI88512C
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA OUT
READ CYCLE 2 (WE HIGH)
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
OE
CS
WS32K32-XHX
FIG. 2
TIMING WAVEFORM - READ CYCLE
FIG. 4
WRITE CYCLE - CS CONTROLLED
FIG. 3
WRITE CYCLE - WE CONTROLLED
ADDRESS
DATA IN
WRITE CYCLE 2, CS CONTROLLED
t
AVEH
t
ELEH
t
EHAX
t
WLEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH Z
WE
CS
DATA OUT
t
AVEL
ADDRESS
DATA IN
WRITE CYCLE 1, WE CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
WE
CS
DATA OUT
5
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI88512C
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
V
DD
V
DD
= 2.0V
2
V
Data Retention Quiescent Current
I
CCDR
CS
V
DD
-0.2V
185
A
Chip Disable to Data Retention Time
T
CDR
V
IN
V
DD
-0.2V
0
ns
Operation Recovery Time
T
R
or V
IN
0.2V
T
AVAV
ns
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)
(T
A
= -55
C to +125
C)
WS32K32-XHX
FIG. 5
DATA RETENTION - CS CONTROLLED
DATA RETENTION, CS CONTROLLED
Data Retention Mode
t
R
Vcc
CS
t
CDR
CS = V
DD
-0.2V
V
DD
4.5V
4.5V
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