EDI8F32256C
256Kx32 SRAM Module
1
EDI8F32256C Rev. 12 9/98 ECO #10816
256Kx32 Static RAM
CMOS, High Speed Module
The EDI8F32256C is a high speed 8 megabit Static RAM
module organized as 256K words by 32 bits. This module is
constructed from eight 256Kx4 Static RAMs in SOJ packages
on an epoxy laminate (FR4) board.
Four chip enables (E-E3) are used to independently enable
the four bytes. Reading or writing can be executed on
individual bytes or any combination of multiple bytes through
proper use of selects.
The EDI8F32256C is offered in 64 pin ZIP/SIMM package
which enables eight megabits of memory to be placed in less
than 1.4 square inches of board space.
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous circuitry requires no
clocks or refreshing for operation and provides equal access
and cycle times for ease of use.
The ZIP and SIMM modules contain two pins, PD1 and PD2,
which are used to identify module memory density in applica-
tions where alternate modules can be interchanged.
Features
256Kx32 bit CMOS Static
Random Access Memory
Access Times
BiCMOS: 10 and 12ns
CMOS: 15, 20, 25, and 35ns
Individual Byte Selects
Fully Static, No Clocks
TTL Compatible I/O
High Density Package with JEDEC Standard Pinouts
64 Pin ZIP, No. 85
64 Lead Angled SIMM, No. 32
64 Lead SIMM, No. 333
64 ZIP Low Profile, No. 188
Common Data Inputs and Outputs
Single +5V (10%) Supply Operation
Pin Names
W
G
E
E1
E2
E3
DQ-DQ3
DQ8-DQ11
DQ16-DQ19
DQ24-DQ27
DQ4-DQ7
DQ12-DQ15
DQ20-DQ23
DQ28-DQ31
4
4
4
4
4
4
4
4
A-A17
Address Inputs
E-E3
Chip Enables
W,
Write Enables
G
Output Enable
DQ-DQ31
Common Data Input/Output
VCC
Power (+5V10%)
VSS
Ground
VSS
PD2
DQ8
DQ9
DQ10
DQ11
A
A1
A2
DQ12
DQ13
DQ14
DQ15
VSS
A15
E1
E3
A17
G
DQ24
DQ25
DQ26
DQ27
A3
A4
A5
VCC
A6
DQ28
DQ29
DQ30
DQ31
PD1
DQ
DQ1
DQ2
DQ3
VCC
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
W
A14
E
E2
A16
VSS
DQ16
DQ17
DQ18
DQ19
A10
A11
A12
A13
DQ20
DQ21
DQ22
DQ23
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
64 Pin
PD1 - VSS
PD2 - VSS
Pin Configurations and Block Diagram
Electronic Designs, Inc.
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
http://www.electronic-designs.com
2
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
Absolute Maximum Ratings*
Recommended DC Operating Conditions
DC Electrical Characteristics
Parameter
Sym
Conditions
Min
Max Max Max
Max Units
10-12 15ns 20 25-35 ns
Operating Power Supply Current
ICC1
W, E = VIL, II/O = 0mA, Min Cycle
1360 1280 1440 1280 mA
Standby (TTL) Power Supply Current ICC2
E VIH, VIN - VIL or VIN VIH
480 240 200
200
mA
Full Standby Power Supply Current
ICC3
E VCC-0.2V
80
80
40
40
mA
CMOS
VIN VCC-0.2V or VIN - 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
--
80 80 80
80
A
Output Leakage Current
ILO
V I/O = 0V to VCC
--
20 20 20
20
A
Output High Voltage
VOH
IOH = -4.0mA
2.4
--
--
--
--
V
Output Low Voltage
VOL
IOL = 8.0mA
--
0.4
0.4
0.4
0.4
V
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Max
Unit
Address Lines
CI
60
pF
Data Lines
CD/Q
20
pF
Chip Enable Line
CC
20
pF
Write Control Line
CN
60
pF
AC Test Conditions
Parameter
Sym
Min
Typ
Max Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-- VCC+0.3V V
Input Low Voltage
VIL
-0.3
--
0.8
V
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL = 30pF
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial.
0C to +70C
Industrial
-40C to +85C
Storage Temperature, Plastic
-55C to +125C
Power Dissipation
8.0 Watt
Output Current.
20 mA
*Typical: TA = 25C, VCC = 5.0V
E
W
G
Mode
Output
Power
H
X
X
Standby
HIGH Z
ICC3
L
H
L
Read
DOUT
ICC1
L
L
X
Write
DIN
ICC1
L
H
H
Output Deselect HIGH Z
ICC1
Truth Table
These parameters are sampled, not 100% tested.
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
EDI8F32256C
256Kx32 SRAM Module
3
EDI8F32256C Rev. 12 9/98 ECO #10816
AC Characteristics Read Cycle
Symbol
10ns*
12ns*
15ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
TAVAV
TRC
10
12
15
ns
Address Access Time
TAVQV
TAA
10
12
15
ns
Chip Enable Access
TELQV
TACS
10
12
15
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
5
6
8
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
5
5
8
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
0
0
0
ns
Output Disable to Output in High Z (1)
TGHQZ
TOHZ
4
4
5
ns
Read Cycle 2 - W High
Note 1: Parameter guaranteed, but not tested. *BICMOS
Read Cycle 1 - W High, G, E Low
TAVAV
TAVQV
TAVQX
DATA 2
A
Q
ADDRESS 1
ADDRESS 2
DATA 1
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
4
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
Symbol
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
TAVAV
TRC
20
25
35
ns
Address Access Time
TAVQV
TAA
20
25
35
ns
Chip Enable Access
TELQV
TACS
20
25
35
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
10
12
15
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
13
15
20
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
0
0
0
ns
Output Disable to Output in High Z(1)
TGHQZ
TOHZ
8
10
12
ns
Note 1: Parameter guaranteed, but not tested.
TAVAV
TAVQV
TAVQX
DATA 2
A
Q
ADDRESS 1
ADDRESS 2
DATA 1
Read Cycle 2 - W High
g
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
Read Cycle 1 - W High, G, E Low
AC Characteristics Read Cycle
EDI8F32256C
256Kx32 SRAM Module
5
EDI8F32256C Rev. 12 9/98 ECO #10816
Symbol
10ns*
12ns*
15ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
TAVAV
TWC
10
12
15
ns
Chip Enable to End of Write
TELWH
TCW
7
8
12
ns
TWLEH
TCW
7
8
10
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
7
8
10
ns
TAVEH
TAW
7
8
10
ns
Write Pulse Width
TWLWH
TWP
7
8
10
ns
TELEH
TWP
7
8
10
ns
Write Recovery Time
TWHAX
TWR
0
0
0
ns
TEHAX
TWR
0
0
0
ns
Data Hold Time
TWHDX
TDH
3
3
3
ns
TEHDX
TDH
3
3
3
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
5
0
6
0
9
ns
Data to Write Time
TDVWH
TDW
5
6
7
ns
TDVEH
TDW
5
6
7
ns
Output Active from End of Write (1)
TWHQX
TWLZ
3
3
3
ns
Note 1: Parameter guaranteed, but not tested.
*BICMOS
Symbol
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
TAVAV
TWC
20
25
35
ns
Chip Enable to End of Write
TELWH
TCW
15
20
30
ns
TWLEH
TCW
15
20
30
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
15
20
30
ns
TAVEH
TAW
15
20
30
ns
Write Pulse Width
TWLWH
TWP
15
20
30
ns
TELEH
TWP
15
20
30
ns
Write Recovery Time
TWHAX
TWR
0
0
0
ns
TEHAX
TWR
0
0
0
ns
Data Hold Time
TWHDX
TDH
3
3
3
ns
TEHDX
TDH
3
3
3
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
10
0
12
0
15
ns
Data to Write Time
TDVWH
TDW
12
15
20
ns
TDVEH
TDW
12
15
20
ns
Output Active from End of Write (1)
TWHQX
TWLZ
3
3
3
ns
Note 1: Parameter guaranteed, but not tested.
AC Characteristics Write Cycle
AC Characteristics Write Cycle
6
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
A
W
E
D
Q
TAVAV
TAVEL
TEHAX
TDVEH
TEHDX
TELEH
TAVEH
DATA VALID
HIGH Z
TWLEH
Write Cycle 1 - W Controlled
Write Cycle 2 - E Controlled
A
E
W
D
Q
TAVAV
TELWH
T A V W H
T W L W H
TAVWL
T D V W H
T W H D X
T W H Q X
HIGH Z
TWLQZ
DATA VALID
T W H A X
EDI8F32256C
256Kx32 SRAM Module
7
EDI8F32256C Rev. 12 9/98 ECO #10816
Part Number
Speed
Package
(ns)
No.
BICMOS
EDI8G32256B10MNC
10
32
EDI8G32256B12MNC
12
32
CMOS
EDI8F32256C15MNC
15
32
EDI8F32256C20MNC
20
32
EDI8F32256C25MNC
25
32
EDI8F32256C35MNC
35
32
BICMOS
EDI8G32256B10MMC
10
333
EDI8G32256B12MMC
12
333
CMOS
EDI8F32256C15MMC
15
333
EDI8F32256C20MMC
20
333
EDI8F32256C25MMC
25
333
EDI8F32256C35MMC
35
333
Package Description
Part Number.
Speed
Package
(ns)
No.
BICMOS
EDI8F32256B10MZC
10
85
EDI8F32256B12MZC
12
85
CMOS
EDI8F32256C15MZC
15
85
EDI8F32256C20MZC
20
85
EDI8F32256C25MZC
25
85
EDI8F32256C35MZC
35
85
Package No. 32
64 Lead Angled SIMM
Package No. 85
64 Pin ZIP
NOTE: 1. For Gold SIMM change form EDI8F to EDI8G.
2. The BICMOS 10 & 12ns SIMMs available with Gold Contacts only.
Ordering Information
P1
.360
MAX.
.225
.125
MIN.
MIN.
3.855 MAX.
3.584
.250
.400
.680
MAX.
.250
.050
3.350
1.845
1.792
R.062. (2x)
.250
TYP.
.022
.018
.050
TYP.
.175
.125
.050
.050
MAX.
.580
MAX.
.165
.135
.100
TYP.
.360
MAX.
.100
TYP.
3.665
Part Number.
Speed
Package
(ns)
No.
CMOS
EDI8F32257C20MZC
20
188
EDI8F32257C25MZC
25
188
8
EDI8F32256C Rev. 12 9/98 ECO #10816
EDI8F32256C
256Kx32 SRAM Module
Electronic Designs, Inc.
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
http://www.electronic-designs.com
Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301
Package No. 333
64 Lead SIMM
3.584
.250
.062 R.
.360
MAX.
.125
MIN.
#
.250
.050 TYP.
.062 R.
.400
.615
MAX.
3.855 MAX.
1.845
1.792
3.350
.125
TYP.
.050
.050
3.665 MAX.
.170
.130
.017
.021
.100 TYP.
.100
TYP.
MAX.
.360
.470
.175
MAX.
.050
Package No. 188
64 ZIP Low Profile
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