ChipFind - документация

Электронный компонент: EDI8F81024C100BSC

Скачать:  PDF   ZIP
EDI8F81024C
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2002
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
The EDI8F81024C is a 8Mb CMOS Static RAM based on eight
128Kx8 Static RAMs mount ed on a multi-layered epoxy laminate
(FR4) substrate.
A version featuring Low Power with Data Retention (EDI8F81024LP)
is also available.
The EDI8F81024C is offered in a double sided, 36 pin single-in-line
Package (SIP). Surface mount SIP tech nol o gy is a cost ef fec tive
so lu tion to very high packing density re quire ments.
All inputs and outputs are TTL compatible and op er ate from a single
5V supply. Fully asyn chro nous, the EDI8F81024C re quires no clocks
or refreshing for op er a tion.
PIN CONFIGURATIONS AND BLOCK DIAGRAM
PIN NAMES
FEATURES
1024Kx8 bit CMOS Static
Random
Access
Memory
Access Times 70 thru 100ns
Data Retention Function (EDI8F81024LP)
TTL Com pat i ble In puts and Outputs
Fully Static, No Clocks
High Density Packaging
36 Pin SIP, No. 62
Single +5V (10%) Supply Operation
*This product is subject to change without notice.
1Mx8 Static RAM CMOS, Module
DESCRIPTION
A-A19
Address Inputs
E#
Chip Enable
W#
Write Enable
G#
Output Enable
DQ-DQ7
Common Data Input/Output
V
CC
Power (+5V10%)
V
SS
Ground
NC
No Connection
NC
V
CC
W#
DQ2
DQ3
DQ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A1
A2
A3
A4
V
SS
DQ5
E#
A15
A16
A12
A18
A6
DQ1
V
SS
A0
A7
A8
A9
DQ7
DQ4
DQ6
A17
V
CC
G#
A10
A11
A5
A13
A14
A19
PIN OUT
A0-A16
W#
G#
A19
A18
A17
E#
DEC
DQ0-DQ7
128K
X 8
128K
X 8
128K
X 8
128K
X 8
128K
X 8
128K
X 8
128K
X 8
128K
X 8
EDI8F81024C
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2002
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
*Typical: T
A
= 25C, V
CC
= 5.0V
TRUTH TABLE
AC TEST CONDITIONS
*Stress greater than those listed under "Ab so lute Maxi mum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional op era tion of the device at these or any other conditions greater
than those in di cated in the operational sections of this speci fi ca tion is not
im plied. Ex po sure to ab so lute maxi mum rating con di tions for ex tended
periods may affect re lia bil ity.
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Voltage on any pin relative to V
SS
-0.5V to 7.0V
Operating Temperature T
A
(Ambient)
Commercial
Industrial
0C to +70C
-40C to +85C
Storage Temperature
Plastic
-55C to +125C
Power Dissipation
1 Watt
Output Current
20 mA
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL = 100pF
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
6.0
V
Input Low Voltage
V
IL
-0.3
0.8
V
CAPACITANCE
(f=1.0MHz, V
IN
=V
CC
or V
SS
)
These parameters are sampled, not 100% tested.
G#
E#
W#
Mode
Output
Power
X
H
X
Standby
HIGH Z
I
CC2
/I
CC3
H
L
H
Output
Deselect
HIGH Z
I
CC1
L
L
H
Read
D
OUT
I
CC1
X
L
L
Write
D
IN
I
CC1
Parameter
Sym
Max
Unit
Input Capacitance
(Except DQ Pins)
CI
58
pF
Capacitance (DQ Pins)
CD/Q
43
pF
Input (E#) Control Lines
CC
10
pF
Input (W#) Line (G#)
CW
60
pF
Parameter
Sym
Conditions
Min
Typ*
Max
Units
Operating Power Supply Current
I
CC1
W#, E# = V
IL
, II/O = 0mA, Min Cycle
80
130
mA
Standby (TTL) Power Supply Current
I
CC2
E#
V
IH
, V
IN
V
IL
or V
IN
V
IH
40
90
mA
Full Standby Power Supply Current
(CMOS)
I
CC3
E#
V
CC
-0.2V
V
IN
V
CC
-0.2V or
V
IN
0.2V
C
LP
10
400
20
950
mA
A
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
10
A
Output Leakage Current
I
LO
V I/O = 0V to V
CC
10
A
Output High Voltage
V
OH
I
OH
= -1.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 2.1mA
0.4
V
EDI8F81024C
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2002
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
R
EAD
C
YCLE
2 - W# H
IGH
READ CYCLE 1 - W# HIGH, G#, E# LOW
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
A
Q
TGHQZ
TELQV
TELQX
E#
G#
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
AC CHARACTERISTICS READ CYCLE
Note 1: Parameter guaranteed, but not tested.
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
TAVAV
TRC
70
85
100
ns
Address Access Time
TAVQV
TAA
70
85
100
ns
Chip Enable Access
TELQV
TACS
70
85
100
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
5
5
5
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
30
35
40
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
40
45
50
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
0
0
0
ns
Output Disable to Output in High Z(1)
TGHQZ
TOHZ
30
35
40
ns
EDI8F81024C
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2002
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS WRITE CYCLE
E#
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W#
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
WRITE CYCLE 1 - W# CON TROLLED
Note 1: Parameter guaranteed, but not tested.
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
TAVAV
TWC
70
85
100
ns
Chip Enable to End of Write
TELWH
TELEH
TCW
TCW
65
65
70
70
80
80
ns
ns
Address Setup Time
TAVWL
TAVEL
TAS
TAS
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
TAVWH
TAVEH
TAW
TAW
65
65
70
70
80
80
ns
ns
Write Pulse Width
TWLWH
TWLEH
TWP
TWP
65
65
70
70
80
80
ns
ns
Write Recovery Time
TWHAX
TEHAX
TWR
TWR
0
0
0
0
0
0
ns
ns
Data Hold Time
TWHDX
TEHDX
TDH
TDH
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
30
0
35
0
40
ns
Data to Write Time
TDVWH
TDVEH
TDW
TDW
30
30
35
35
40
40
ns
ns
Output Active from End of Write (1)
TWHQX
TWLZ
5
5
5
ns
EDI8F81024C
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2002
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
WRITE CYCLE 2 - E# CON TROLLED
DATA RETENTION E# CON TROLLED
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
Characteristic
Sym
Test Conditions
V
CC
Min
Typ
Max
Unit
Data Retention Voltage
V
CC
V
CC
= 0.2V
70C
85C
2
V
Data Retention Quiescent Current
I
CCDR
E#
V
CC
-0.2V
2V
25
300
400
A
V
IN
V
CC
-0.2V
3V
50
450
550
A
Chip Disable to Data Retention Time (1)
TCDR
or V
IN
0.2V
0
ns
Operation Recovery Time (1)
TR
TAVAV*
ns
A
TAVEL
HIGH Z
TAVAV
TELEH
E#
TAVEH
TEHAX
W#
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D
V
CC
TR
DATA RETENTION MODE
E#
TCDR
E#
VDD-0.2V
V
CC
4.5V
4.5V