1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 6A
ECO #15405
EDI8F82045C
FEATURES
The EDI8F82045C is a 16Mb CMOS Static RAM based on four
512K x 8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
A low power version with data retention (EDI8F82045LP) is also
available.
All inputs and outputs are TTL compatible and operate from a
single 5V supply.
Fully asynchronous, the EDI8F82045C requires no clocks or
refreshing for operation.
n 2Mx8 bit CMOS Static
n Random Access Memory
Access Times 70 thru 100ns
Data Retention Function (EDI8F82045LP )
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
High Density Packaging
36 Pin DIP, No. 177
Single +5V (10%) Supply Operation
P
IN
N
AMES
P
IN
C
ONFIGURATIONS
AND
B
LOCK
D
IAGRAM
n
n
DESCRIPTION
A-A20
Address Inputs
E
Chip Enable
W
Write Enable
G
Output Enable
DQ-DQ7
Common Data Input/Output
VCC
Power (+5V10%)
VSS
Ground
NC
No Connection
FIG. 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
A19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
8F82045C Pin Config
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC
A20
NC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DQ
0-7
512K x 8
512K x 8
512K x 8
512K x 8
A
0-18
W
G
A
19-20
E
DEC
8F82045C Blk Dia
2Mx8 STATIC RAM CMOS, MODULE
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 6A
ECO #15405
EDI8F82045C
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
DC E
LECTRICAL
C
HARACTERISTICS
C
APACITANCE
T
RUTH
T
ABLE
These parameters are sampled, not 100% tested.
AC T
EST
C
ONDITIONS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Industrial
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
1 Watt
Output Current.
20 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
--
6.0
V
Input Low Voltage
VIL
-0.3
--
0.8
V
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL =100pF
(Note: For TEHQZ, TGHQZ and TWLQZ, CL = 5pF)
*Typical: TA = 25 C, VCC = 5.0V
G
E
W
Mode
Output
Power
X
H
X
Standby
High Z
ICC2, ICC3
H
L
H
Output Deselect
High Z
ICC1
L
L
H
Read
DOUT
ICC1
X
L
L
Write
DIN
ICC1
Parameter
Sym
Max
Unit
Address Lines
CI
30
pF
Data Lines
CD/Q
43
pF
Chip Enable Line
CC
10
pF
Write and Output Enable Lines
CW
32
pF
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Conditions
Min
Typ*
Max
Units
Operating Power
ICC1
W, E = VIL, II/O = 0mA,
--
150
mA
Supply Current
Min Cycle
Standby (TTL) Power
ICC2
E > VIH, VIN < VIL
--
55
mA
Supply Current
VIN > VIH
Full Standby Power
ICC3
E > VCC-0.2V
C
--
2
3
mA
Supply Current (CMOS)
VIN > VCC-0.2V or
LP
--
450
600
A
VIN < 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
-10
--
10
A
Output Leakage Current
ILO
V I/O = 0V to VCC
-10
--
10
A
Output High Voltage
VOH
IOH =-1.0mA
2.4
--
--
V
Output Low Voltage
VOL
IOL = 2.1mA
--
--
0.4
V
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 6A
ECO #15405
EDI8F82045C
AC C
HARACTERISTICS
R
EAD
C
YCLE
R
EAD
C
YCLE
2 - W H
IGH
NOTE 1: Parameter guaranteed, but not tested.
R
EAD
C
YCLE
1 - W H
IGH
, G, E L
OW
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min Max
Min Max
Units
Read Cycle Time
TAVAV
TRC
70
85
100
ns
Address Access Time
TAVQV
TAA
70
85
100
ns
Chip Enable Access Time
TELQV
TACS
70
85
100
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
5
5
5
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
30
35
40
ns
Output Hold from Address Change
TAVQX
TOH
5
5
5
ns
Output Enable to Output Valid
TGLQV
TOE
40
45
50
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
5
5
5
ns
Output Disable to Output in High Z(1)
TGHQZ
TOHZ
30
35
40
ns
FIG. 2
FIG. 3
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
8F82045C Rd Cyc1
A
Q
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
8F82045C Rd Cyc2
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 6A
ECO #15405
EDI8F82045C
Note 1: Parameter guaranteed, but not tested.
W
RITE
C
YCLE
1 - W C
ONTROLLED
AC C
HARACTERISTICS
W
RITE
C
YCLE
Write Cycle
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min Max
Min Max
Units
Write Cycle Time
TAVAV
TWC
70
85
100
ns
Chip Enable to End of Write
TELWH
TCW
65
70
80
ns
TELEH
TCW
65
70
80
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
65
70
80
ns
TAVEH
TAW
65
70
80
ns
Write Pulse Width
TWLWH
TWP
65
70
80
ns
TWLEH
TWP
65
70
80
ns
Write Recovery Time
TWHAX
TWR
5
5
5
ns
TEHAX
TWR
5
5
5
ns
Data Hold Time
TWHDX
TDH
0
0
0
ns
TEHDX
TDH
0
0
0
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
30
0
35
0
40
ns
Data to Write Time
TDVWH
TDW
30
35
40
ns
TDVEH
TDW
30
35
40
ns
Output Active from End of Write (1)
TWHQX
TWLZ
5
5
5
ns
FIG. 4
E
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
8F82045C Write Cyc1
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 6A
ECO #15405
EDI8F82045C
D
ATA
R
ETENTION
- E C
ONTROLLED
D
ATA
R
ETENTION
C
HARACTERISTICS
LP Version Only
W
RITE
C
YCLE
2 - E C
ONTROLLED
FIG. 5
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
FIG. 6
A
TAVEL
HIGH Z
TAVAV
8F82045C Write Cyc2
TELEH
E
TAVEH
TEHAX
W
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D
VCC
TR
8F82045C Data Retent.
DATA RETENTION MODE
E
TCDR
E
VDD-0.2V
VDD
4.5V
4.5V
Characteristic
Sym
Test Conditions
VDD
Min
Typ
Max
Unit
70C 85C
Data Retention Voltage
VDD
2
--
--
--
V
Data Retention Quiescent Current
ICCDR
E > VDD -0.2V
2V
--
200
260
A
VIN > VDD -0.2V
3V
320
420
A
Chip Disable to Data Retention Time TCDR(1)
or VIN 0.2V
0
--
--
--
ns
Operation Recovery Time
TR(1)
TAVAV*
--
--
--
ns
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