EDI8G32130C
128Kx32 SRAM Module
1
EDI8G32130C Rev. 0 1/98 ECO #9700
128Kx32 Static RAM
CMOS, High Speed Module
Features
128Kx32 bit CMOS Static
Random Access Memory
Access Times
BiCMOS: 10 and12ns
CMOS: 15, 20, 25ns
Individual Byte Selects
Fully Static, No Clocks
TTL Compatible I/O
High Density Package
JEDEC Standard Pinouts
72 Pad SIMM, No. 405
Common Data Inputs and Outputs
Single +5V (10%) Supply Operation
Pin Configurations and Block Diagram
The EDI8G32130C is a high speed 4 megabit Static RAM
module organized as 128K words by 32 bits. This module is
constructed from four 128Kx8 Static RAMs in SOJ pack-
ages on an epoxy laminate (FR4) board.
Four chip enables (E-E3) are used to independently
enable the four bytes. Reading or writing can be executed
on individual bytes or any combination of multiple bytes
through proper use of enables.
The EDI8G32130C is offered in a 72 Pad SIMM package,
which enables four megabits of memory to be placed in less
than 1.3 square inches of board space.
All inputs and outputs are TTL compatible and operate from
a single 5V supply. Fully asynchronous circuitry requires no
clocks or refreshing for operation and provides equal access
and cycle times for ease of use.
Four pins, PD1 to PD4, are used to identify module memory
density in applications where alternate modules can be
interchanged.
PD1=Open
PD2=Open
PD3 = Open
PD4 = Vss
Pin Names
A-A16
Address Inputs
E-E3
Chip Enables
W
Write Enable
G
Output Enable
DQ-DQ31
Common Data Input/Output
VCC
Power (+5V10%)
VSS
Ground
NC
No Connection
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX: 01276 473748
http://www.electronic-designs.com
32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
NC
NC
PD3
PD4
VSS
PD1
PD2
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
A0
A7
A1
A8
A2
A9
DQ12
DQ4
DQ5
DQ6
DQ7
DQ13
DQ14
DQ15
VSS
W\
A15
A14
E1\
E0\
1
2
3
4
5
6
7
8
9
64
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
65
66
67
68
69
70
71
72
E3\
E2\
A16
VSS
DQ16
DQ17
DQ18
DQ19
A10
A11
A12
G\
DQ24
DQ25
DQ26
DQ27
A3
A4
A5
VCC
A6
DQ28
DQ29
DQ30
DQ31
A13
DQ20
DQ21
DQ22
DQ23
VSS
NC
NC
NC
NC
NC
A-A16
W
G
E
E1
E2
E3
DQ-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
17
8
8
8
8
2
EDI8G32130C Rev. 0 1/98 ECO #9700
EDI8G32130C
128Kx32 SRAM Module
Absolute Maximum Ratings*
Recommended DC Operating Conditions
DC Electrical Characteristics
Parameter
Sym
Conditions
Min
Max
Units
Operating Power
ICC1
W, E = VIL, II/O = 0mA,
Supply Current
Min Cycle
680
mA
Standby (TTL) Power
ICC2
E
VIH, VIN
VIL or
Supply Current
VIN
VIH
120
mA
Full Standby Power
ICC3
E
VCC-0.2V
40
mA
Supply Current CMOS
VIN
VCC-0.2V or VIN
0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
20
A
Output Leakage Current
ILO
V I/O = 0V to VCC
20
A
Output High Voltage
VOH
IOH = -4.0mA
2.4
--
V
Output Low Voltage
VOL
IOL = 8.0mA
--
0.4
V
*Typical: TA = 25C, VCC = 5.0V
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Max
Unit
Address Lines
CI
45
pF
Data Lines
CD/Q
20
pF
Chip Enable Line
CC
20
pF
Write Line
CN
45
pF
AC Test Conditions
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL = 30pF
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Storage Temperature
-55C to +125C
Power Dissipation
4 Watts
Output Current
20 mA
Parameter
Sym
Min
Typ
Max Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
--
6.0
V
Input Low Voltage
VIL
-0.3
--
0.8
V
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
E
W
G
Mode
Output
Power
H
X
X
Standby
HIGH Z
ICC2/ICC3
L
H
L
Read
DOUT
ICC1
L
L
X
Write
DIN
ICC1
Output
L
H
H
Deselect
HIGH Z
ICC1
These parameters are sampled, not 100% tested.
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance
Truth Table
EDI8G32130C
128Kx32 SRAM Module
3
EDI8G32130C Rev. 0 1/98 ECO #9700
AC Characteristics Read Cycle
Note 1: Parameter guaranteed, but not tested. *BICMOS
Read Cycle 1 - W High, G, E Low
Read Cycle 2 - W High
Symbol
10ns*
12ns*
15ns
20ns
25ns
Parameter
JEDEC Alt.
Min Max
Min Max Min Max
Min Max
Min Max Units
Read Cycle Time
TAVAV TRC
10
12
15
20
25
ns
Address Access Time
TAVQV TAA
10
12
15
20
25
ns
Chip Enable Access
TELQV TACS
10
12
15
20
25
ns
Chip Enable to Output in Low Z (1)
TELQX TCLZ
3
3
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ TCHZ
5
6
8
10
12
ns
Output Hold from Address Change
TAVQX TOH
3
3
3
3
3
ns
Output Enable to Output Valid
TGLQV TOE
5
5
6
13
15
ns
Output Enable to Output in Low Z (1)
TGLQX TOLZ
0
0
0
0
0
ns
Output Disable to Output in High Z(1)
TGHQZ TOHZ
4
4
5
8
10
ns
TAVAV
TAVQV
TAVQX
DATA 2
A
Q
ADDRESS 1
ADDRESS 2
DATA 1
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
4
EDI8G32130C Rev. 0 1/98 ECO #9700
EDI8G32130C
128Kx32 SRAM Module
Note 1: Parameter guaranteed, but not tested. *BICMOS
AC Characteristics Write Cycle
Write Cycle 1 - W Controlled
Symbol
10ns*
12ns*
15ns
20ns
25ns
Parameter
JEDEC Alt.
Min Max
Min Max Min Max
Min Max
Min Max Units
Write Cycle Time
TAVAV TWC
10
12
15
20
25
ns
Chip Enable to End of Write
TELWH TCW
7
8
10
15
20
ns
TWLEH TCW
7
8
10
15
20
ns
Address Setup Time
TAVWL TAS
0
0
0
0
0
ns
TAVEL TAS
0
0
0
0
0
ns
Address Valid to End of Write
TAVWH TAW
7
8
10
15
20
ns
TAVEH TAW
7
8
10
15
20
ns
Write Pulse Width
TWLWH TWP
7
8
10
15
20
ns
TELEH TWP
7
8
10
15
20
ns
Write Recovery Time
TWHAX TWR
0
0
0
0
0
ns
TEHAX TWR
0
0
0
0
0
ns
Data Hold Time
TWHDX TDH
3
3
3
3
3
ns
TEHDX TDH
3
3
3
3
3
ns
Write to Output in High Z (1)
TWLQZ TWHZ
0
5
0
6
0
7
0
10
0
12
ns
Data to Write Time
TDVWH TDW
5
6
7
12
15
ns
TDVEH TDW
5
6
7
12
15
ns
Output Active from End of Write (1)
TWHQX TWLZ
2
2
2
3
3
ns
A
E
W
D
Q
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TDVWH
TWHDX
TWHQX
HIGH Z
TWLQZ
DATA VALID
TWHAX
EDI8G32130C
128Kx32 SRAM Module
5
EDI8G32130C Rev. 0 1/98 ECO #9700
Write Cycle 2 - E Controlled
A
W
E
D
Q
TAVAV
TAVEL
TEHAX
TDVEH
TEHDX
TELEH
TAVEH
DATA VALID
HIGH Z
TWLEH
Package Description
Ordering Information
Package No. 405
72 pad SIMM
Part Number
Speed (ns)
Package No.
BiCMOS
EDI8G32130B10MMC
10
405
EDI8G32130B12MMC
12
405
Part Number
Speed (ns)
Package No.
CMOS
EDI8G32130C15MMC
15
405
EDI8G32130C20MMC
20
405
EDI8G32130C25MMC
25
405
3.984
.400
.625
MAX.
.250
.050 TYP.
3.750
2.045
1.992
.250
.125 DIA. (2x)
.062 R. (2x)
.125
MIN.
.213 MAX.
4.255 MAX.
P1
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX: 01276 473748
http://www.electronic-designs.com
Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301
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