EDI8F32512C
512Kx32 SRAM Module
1
EDI8F32512C Rev. 7 12/97 ECO #9492
Features
512Kx32 bit CMOS Static
Random Access Memory
Access Times: 15, 17, 20, 25 and 35ns
Individual Byte Selects
Fully Static, No Clocks
TTL Compatible I/O
High Density Package
72 Pin ZIP, No. 173
72 lead SIMM, No. 174 (Gold Option)
Common Data Inputs and Outputs
Single +5V (10%) Supply Operation
The EDI8F32512C is a high speed 16 megabit Static RAM module
organized as 512K words by 32 bits. This module is constructed
from four 512Kx8 Static RAMs in SOJ packages on an epoxy
laminate (FR4) board.
Four chip enables (E-E3) are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes
or any combination of multiple bytes through proper use of selects.
The EDI8F32512C is offered in 72 pin ZIP and 72 lead SIMM
packages, which enable 16 megabits of memory to be placed in
less than 1.3 square inches of board space.
All inputs and outputs are TTL compatible and operate from a single
5V supply. Fully asynchronous circuitry requires no clocks or
refreshing for operation and provides equal access and cycle times
for ease of use.
Pins PD1- PD4, are used to identify module memory density in
applications where alternate modules can be interchanged.
NC
PD3
VSS
PD2
DQ8
DQ9
DQ10
DQ11
A
A1
A2
DQ12
DQ13
DQ14
DQ15
VSS
A15
E1
E3
A17
G
DQ24
DQ25
DQ26
DQ27
A3
A4
A5
VCC
A6
DQ28
DQ29
DQ30
DQ31
A18
NC
NC
PD4
PD1
DQ
DQ1
DQ2
DQ3
VCC
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
W
A14
E
E2
A16
VSS
DQ16
DQ17
DQ18
DQ19
A10
A11
A12
A13
DQ20
DQ21
DQ22
DQ23
VSS
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
PD1, PD2,PD4 = Open
PD3 = VSS
A-A18
W
G
E
E1
E2
E3
DQ-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
19
8
8
8
8
Pin Configurations and Block Diagram
Pin Names
512Kx32 Static RAM
CMOS, High Speed Module
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581 USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX 01276 473748
http://www.electronic-designs.com
A-A18
Address Inputs
E-E3
Chip Enables
W
Write Enable
G
Output Enable
DQ-DQ31
Common Data
Input/Output
VCC
Power (+5V10%)
VSS
Ground
NC
No Connection
2
EDI8F32512C Rev. 7 12/97 ECO #9492
EDI8F32512C
512Kx32 SRAM Module
Absolute Maximum Ratings*
Recommended DC Operating Conditions
DC Electrical Characteristics
Parameter
Sym
Conditions
Min
Typ*
Max
Units
Operating Power Supply Current
ICC1 W, E = VIL, II/O = 0mA, Min Cycle
800
mA
Standby (TTL) Power Supply Current ICC2
E
VIH, VIN
VIL or VIN
VIH
300
mA
Full Standby Power Supply Current
ICC3
E
VCC-0.2V
80
mA
CMOS
VIN
VCC-0.2V or VIN
0.2V
(BiCMOS)
120
mA
Input Leakage Current
ILI
VIN = 0V to VCC
--
--
20
A
Output Leakage Current
ILO
V I/O = 0V to VCC
--
--
20
A
Output High Voltage
VOH
IOH = -4.0mA
2.4
--
--
V
Output Low Voltage
VOL
IOL = 8.0mA
--
--
0.4
V
Capacitance
Truth Table
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Max
Unit
Address Lines
CI
45
pF
Data Lines
CD/Q
20
pF
Chip Enable Line
CC
20
pF
Write Line
CN
45
pF
AC Test Conditions
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Parameter
Sym
Min
Typ
Max Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
--
6.0
V
Input Low Voltage
VIL
-0.3
--
0.8
V
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL = 30pF
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Industrial
-40C to +85C
Storage Temperature, Plastic
-55C to +125C
Power Dissipation
5.0 Watts
Output Current
20 mA
*Typical: TA = 25C, VCC = 5.0V
E
W
G
Mode
Output
Power
H
X
X
Standby
HIGH Z
ICC2/ICC3
L
H
L
Read
DOUT
ICC1
L
L
X
Write
DIN
ICC1
Output
L
H
H
Deselect
HIGH Z
ICC1
These parameters are sampled, not 100% tested.
EDI8F32512C
512Kx32 SRAM Module
3
EDI8F32512C Rev. 7 12/97 ECO #9492
AC Characteristics Read Cycle
Symbol
15ns
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min Max
Min Max
Min Max
Min Max
Min Max Units
Read Cycle Time
TAVAV
TRC
15
17
20
25
35
ns
Address Access Time
TAVQV
TAA
15
17
20
25
35
ns
Chip Enable Access
TELQV
TACS
15
17
20
25
35
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
3
3
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
6
7
10
12
15
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
6
6
8
10
12
ns
Output Enable to Output in Low Z (1) TGLQX
TOLZ
0
0
0
0
0
ns
Output Disable to Output in High Z(1) TGHQZ
TOHZ
6
7
8
10
12
ns
Read Cycle 2 - W High
Read Cycle 1 - W High, G, E Low
Notes: 1. Parameter guaranteed, but not tested.
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TGLQV
TGLQX
TAVQV
TAVAV
TAVQV
TAVQX
DATA 2
A
Q
ADDRESS 1
ADDRESS 2
DATA 1
4
EDI8F32512C Rev. 7 12/97 ECO #9492
EDI8F32512C
512Kx32 SRAM Module
Notes: 1. Parameter guaranteed, but not tested.
Symbol
15ns
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min Max
Min Max
Min Max
Min Max
Min Max Units
Write Cycle Time
TAVAV
TWC
15
17
20
25
35
ns
Chip Enable to End of Write
TELWH
TCW
8
12
15
20
25
ns
TWLEH
TCW
8
12
15
20
25
ns
Address Setup Time
TAVWL
TAS
0
0
0
0
0
ns
TAVEL
TAS
0
0
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
8
12
15
15
20
ns
TAVEH
TAW
8
12
15
15
20
ns
Write Pulse Width
TWLWH
TWP
10
12
15
15
20
ns
TELEH
TWP
10
12
15
15
20
ns
Write Recovery Time
TWHAX
TWR
0
0
0
0
0
ns
TEHAX
TWR
0
0
0
0
0
ns
Data Hold Time
TWHDX
TDH
0
0
0
0
0
ns
TEHDX
TDH
0
0
0
0
0
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
6
0
8
0
8
0
12
0
15
ns
Data to Write Time
TDVWH
TDW
7
8
9
10
20
ns
TDVEH
TDW
7
8
9
10
20
ns
Output Active from End of Write (1) TWHQX
TWLZ
3
3
3
3
3
ns
AC Characteristics Write Cycle
Write Cycle 1 - W Controlled
A
E
W
D
Q
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TDVWH
TWHDX
TWHQX
HIGH Z
TWLQZ
DATA VALID
TWHAX
EDI8F32512C
512Kx32 SRAM Module
5
EDI8F32512C Rev. 7 12/97 ECO #9492
Write Cycle 2 - E Controlled
A
W
E
D
Q
TAVAV
TAVEL
TEHAX
TDVEH
TEHDX
TELEH
TAVEH
DATA VALID
HIGH Z
TWLEH
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