EDI8L24128C
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
128Kx24 Asynchronous SRAM, 5V
DESCRIPTION
The EDI8L24128CxxBC is a 5V, three megabit SRAM
constructed with three 128Kx8 die mounted on a multi-
layer laminate substrate. With 12 to 15ns access times, x24
width and a 5V operating voltage, the EDI8L2418C is ideal
for creating a single chip memory solution for the Motorola
DSP5600x or a two chip solution for the Analog Devices
SHARCTM DSP.
The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices. For example, the capacitance
load on the data lines for the BGA package is 58% less than
a monolithic SOJ solution.
The JEDEC Standard 119 lead BGA provides a 44% space
savings over using 128Kx8, 300mm wide SOJs and the
BGA package has a height of 100mm compared to 148mm
for the SOJ packages.
FEATURES
128Kx24 bit CMOS Static
Random Access Memory Array
Fast Access Times: 12 and 15ns
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mm x 22mm
Multiple Ground Pins for Maximum Noise
Immunity
Single +5V (10%) Supply Operation
DSP Memory Solution
Motorola DSP5600xTM
Analog Devices SHARCTM
FIG. 1 PIN CONFIGURATION
Pin DESCRIPTION
1
2
3
4
5
6
7
A
NC
A
0
A
1
A
2
A
3
A
4
NC
B
NC
A
5
A
6
E
A
7
A
8
NC
C
DQ
12
NC
NC
NC
NC
NC
DQ
0
D
DQ
13
V
CC
GND GND GND
V
CC
DQ
1
E
DQ
14
GND V
CC
GND V
CC
GND DQ
2
F
DQ
15
V
CC
GND GND GND
V
CC
DQ
3
G
DQ
16
GND V
CC
GND V
CC
GND DQ
4
H
DQ
17
V
CC
GND GND GND
V
CC
DQ
5
I
NC
GND V
CC
GND V
CC
GND
NC
J
DQ
18
V
CC
GND GND GND
V
CC
DQ
6
K
DQ
19
GND V
CC
GND V
CC
GND DQ
7
L
DQ
20
V
CC
GND GND GND
V
CC
DQ
8
M
DQ
21
GND V
CC
GND V
CC
GND DQ
9
N
DQ
22
V
CC
GND GND GND
V
CC
DQ
10
O
DQ
23
NC
NC
NC
NC
NC
DQ
11
P
NC
A
9
A
10
W
A
11
A
12
NC
Q
NC
A
13
A
14
G
A
15
A
16
NC
A0-16
Address Inputs
E#
Chip Enables
W#
Master Write Enable
G3
Master Output Enable
DQ0-23
Common Data
Input/Output
V
CC
Power (+5V10%)
GND
Ground
NC
No Connection
A0-A16
G#
W#
E#
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
128K x 24
Memory
Array
EDI8L24128C
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
Absolute Maximum Ratings*
Recommended Operating Conditions
Voltage on any pin relative to V
SS
-0.5V to 7.0V
Operating Temperature T
S
(Ambient)
Commercial
Industrial
0C to + 70C
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
3 Watts
Output Current.
20 mA
Junction Temperature, T
J
175C
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(Vcc = 5V, T
A
= 25C)
Capacitance
(f=1.0
MHZ
, V
IN
=V
CC
OR
V
SS
)
Note: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
V
CC
+0.3
V
Input Low Voltage
V
IL
-0.3
--
+0.8
V
AC Test Conditions
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing
Levels
1.5V
Output Load
Figure 1
Parameter
Symbol
Max
Unit
Address Lines
C
L
8
pf
Data Lines
C
D
/
Q
10
pf
Write & Output Enable Line
W#, G#
8
pf
Chip Enable Lines
E#
8
pf
Truth Table
E#
W#
G#
Mode
Output
Power
H
X
X
Standby
High Z
I
CC
2
, I
CC
3
L
H
H
Output Deselect
High Z
I
CC
1
L
H
L
Read
Data Out
I
CC
1
L
L
X
Write
Data In
I
CC
1
Parameter
Symbol
Conditions
Min
Type
Max
Units
Operating Power Supply Current
I
CC
1
W# = V
IL
, I
I
/
O
= 0mA, Min Cycle
200
270
mA
Standby (TTL) Power Supply Current
I
CC
2
E# V
IH
, V
IN
V
IL
or V
IN
V
IH
,
f = 0MHz
45
mA
Full Standby Power CMOS
I
CC
3
E# V
CC
-0.2V
10
mA
Supply Current
V
IN
V
CC
-0.2V or V
IN
0.2V
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
--
--
10
A
Output Leakage Current
I
LO
V
I
/
O
0V to V
CC
--
--
10
A
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
--
--
V
Output Low Voltage
V
OL
I
OL
= 8.0mA
--
--
0.4
V
Fig. 1
Fig. 2
D
OUT
30pf
V
L
=1.5V
R
L
= 50
Z0= 50
D
OUT
480
255
5pf
V
cc
EDI8L24128C
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
AC Characteristics Read Cycle
Parameter
Symbol
12ns
15ns
Units
JEDEC Alt.
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
12
15
ns
Address Access Time
t
AVQV
t
AA
12
15
ns
Chip Enable Access Time
t
ELQV
t
ACS
12
15
ns
Chip Enable to Output in Low Z
1
t
ELQX
t
CLZ
3
3
ns
Chip Disable to Output in High Z
1
t
EHQZ
t
CHZ
6
7
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
6
7
ns
Output Enable to Output in Low Z
1
t
GLQX
t
OLZ
0
0
ns
Output Disable to Output in High Z
1
t
GHQZ
t
OHZ
6
7
ns
1. This parameter is guaranteed by design but not tested.
Parameter
Symbol
12ns
15ns
Units
JEDEC
Alt.
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
WC
12
15
ns
Chip Enable to End of Write
t
ELWH
t
ELEH
t
CW
t
CW
9
9
9
9
ns
ns
Address Setup Time
t
AVWL
t
AVEL
t
AS
t
AS
0
0
0
0
ns
ns
Address Valid to End of Write
t
AVWH
t
AVEH
t
AW
t
AW
9
9
10
10
ns
ns
Write Pulse Width
t
WLWH
t
ELEH
t
WP
t
WP
10
10
11
11
ns
ns
Write Recovery Time
t
WHAX
t
EHAX
t
WR
t
WR
0
0
0
0
ns
ns
Data Hold Time
t
WHDX
t
EHDX
t
DH
t
DH
0
0
0
0
ns
ns
Write to Output in High Z
1
t
WLQZ
t
WHZ
0
6
0
7
ns
Data to Write Time
t
DVWH
t
DVEH
t
DW
t
DW
6
6
7
7
ns
ns
Output Active from End of Write
1
t
WHQX
t
WLZ
3
3
ns
AC Characteristics Write Cycle
1. This parameter is guaranteed by design but not tested.
EDI8L24128C
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
FIG. 3
WRITE CYCLE -- W# CONTROLLED
FIG. 4
WRITE CYCLE -- E# CONTROLLED
E#
A
t
AVAV
t
ELWH
t
AVWH
t
WLWH
t
AVWL
t
WHAX
W#
HIGH Z
DATA VALID
t
WLQZ
t
WHQX
t
DVWH
t
WHDX
Q
D
A
t
AVEL
HIGH Z
t
AVAV
t
ELEH
E#
t
AVEH
t
EHAX
W#
t
WLEH
t
EHDX
t
DVEH
Q
DATA VALID
D
ADDRESS 1
ADDRESS 2
t
AVAV
DATA 1
DATA 2
t
AVQV
t
AVQX
A
Q
FIG. 2
TIMING WAVEFORM -- READ CYCLE
t
GHQZ
t
ELQV
t
ELQX
E#
G#
Q
t
EHQZ
A
t
AVAV
t
GLQV
t
GLQX
t
AVQV
Read Cycle 2 (W# High)
Read Cycle 1 (W# High; G, E Low)
EDI8L24128C
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
0.866
BSC
PIN 1
INDEX
0.551
BSC
0.110
MAX.
0.028
MAX.
R.060 MAX.
(4x)
0.050
TYP
0.800
BSC
0.300
BSC
PACKAGE 391:
119 LEAD BGA JEDEC MO-163
ORDERING INFORMATION
Part Number
Speed
(ns)
Package
No.
EDI8L24128C12BI
12
391
EDI8L24128C15BI
15
391
Industrial (-40C to +85C)
ALL DIMENSIONS ARE IN INCHES
Part Number
Speed
(ns)
Package
No.
EDI8L24128C12BC
12
391
EDI8L24128C15BC
15
391
Commercial (0C to +70C)
PDF 
ZIP