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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32128C
August, 2002
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
128Kx32 CMOS High Speed Static RAM
128Kx32 bit CMOS Static
Random Access Memory Array
Fast Access Times: 12, 15, 17, 20, and 25ns
Individual Byte Enables
User Configurable Organization with Minimal
Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 (JEDEC MO-47AE)
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise
Immunity
Single +5V (5%) Supply Operation
The EDI8L32128C is a high speed, high performance,
four megabit density Static RAM organized as a 128Kx32
bit array.
Four Chip Enables, Write Control, and Output Enable
provide the user with a flexible memory solution. The user
may independently enable each of the four bytes, and,
with minimal additional peripheral logic, the unit may be
configured as a 256Kx16 or 512Kx8 array.
Fully asynchronous circuitry is used, requiring no clocks or
refreshing for operation and providing equal access and
cycle times for ease of use.
The EDI8L32128C, allows 4 megabits of memory to be
placed in less than 0.990 square inches of board space; a
savings of 0.885 square inches over four standard 128Kx8
components.
NOTE: Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are word select pins.
BLOCK DIAGRAM
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
A-16
Address Inputs
E-3#
Chip Enables (One per Byte)
W#
Master Write Enable
G#
Master Output Enable
DQ-31
Common Data Input/Output
V
CC
Power (+5V5%)
V
SS
Ground
NC
No Connection
TOP VIEW
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
128Kx32
Memory
Array
A0-A16
G#
W#
E0#
E1#
E2#
E3#
17
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
DQ24
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
V
SS
DQ3
DQ2
DQ1
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DQ31
A6 A5 A4 A3 A2 A1 A0 V
CC
A13 A12 A1
1
A10 A9 A8 A7 DQ0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
DQ16 NC NC E3# E2# E1# E0# NC V
CC
NC NC G# W# A16 A15 A14 DQ15
FEATURES
DESCRIPTION
NOTE: Solder Reflow temperature should not exceed 230C
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32128C
August, 2002
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(f = 1.0MH
Z
, V
IN
= V
CC
or V
SS
)
AC TEST CONDITIONS
DC ELECTRICAL CHARACTERISTICS
Voltage on any pin relative to V
SS
-0.5V to 7.0V
Operating Temperature T
A
(Ambient)
Commercial
Industrial
0C to + 70C
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
4 Watts
Output Current.
20 mA
Junction Temperature, T
J
175C
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
4.75
5.0
5.25
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
V
CC
+0.5
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
Parameter
Sym
Max
Unit
Address Lines
C
A
40
pF
Data Lines
C
D/Q
10
pF
Write & Output Enable Lines
W#, G#
40
pF
Chip Enable Lines/Byte Select
E0-3#
8
pF
TRUTH TABLE
E#
W#
G#
Mode
Output
Power
H
X
X
Standby
High Z I
CC2
,I
CC3
L
H
H
Output Disable
High Z
I
CC1
L
X
X
Output Disable
High Z
I
CC1
L
H
L
Read
D
OUT
I
CC1
L
L
X
Write
D
IN
I
CC1
Parameter
Sym
Conditions
Typ
Max
Units
12*
15
17
20/25
Operating Power Supply Current
I
CC1
W# = V
IL
, II/O = 0mA,
Min Cycle
620
720
680
640
600
mA
Standby (TTL) Supply Current
I
CC2
E# V
IH
, V
IN
V
IL
or
V
IN
V
IH
, f = MH
Z
160
160
160
160
mA
Full Standby CMOS Supply Current
I
CC3
E# V
CC
-0.2V
V
IN
V
CC
-0.2V or
V
IN
0.2V
20
20
20
20
mA
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
10
A
Output Leakage Current
I
LO
V I/O = 0V to V
CC
10
A
Output High Volltage
V
OH
I
OH
= -4.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 8.0mA
0.4
V
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 2
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 3)
Typical: T
A
= 25C, V
CC
= 5.0V
Figure 2
Figure 3
V
CC
Q
480
30 pF
255
V
CC
Q
480
5 pF
255
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32128C
August, 2002
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 4 READ CYCLE 1 - W# HIGH, G#, E# LOW
AC CHARACTERISTICS - READ CYCLE
Parameter
Symbol
12ns
15ns
17ns
20ns
25n
Units
JEDEC Alt.
Min Max
Min Max Min Max
Min
Max Min
Max
Read Cycle Time
t
AVAV
t
RC
12
15
17
20
25
ns
Address Access Time
t
AVQV
t
AA
12
15
17
20
25
ns
Chip Enable Access Time
t
ELQV
t
ACS
12
15
17
20
25
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
2
3
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
7
8
8
10
10
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
3
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
5
6
8
8
10
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
2
2
2
2
0
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
4
5
6
8
10
ns
NOTE 1: Parameter guaranteed, but not tested.
FIG. 5 READ CYCLE 2 - W# HIGH
A
Q
t
AVAV
ADDRESS 1
t
AVQV
t
AVQX
DATA 1
ADDRESS 2
DATA 2
A
E#
G#
Q
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
GLQV
t
GLQX
t
EHQZ
t
GHQZ
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32128C
August, 2002
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
A
G#
E#
W#
D
Q
t
AVAV
t
AVWH
t
ELWH
t
WLWH
t
AVWL
t
GLAX
t
WHAX
t
DVWH
t
WHDX
t
WLQZ
HIGH Z
t
WHQX
DATA VALID
FIG. 7 WRITE CYCLE 2 - E# CONTROLLED
FIG. 6 WRITE CYCLE 1 - W# CONTROLLED
Parameter
Symbol
12ns
15ns
17ns
20ns
25ns
Units
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
WC
12
15
17
20
25
ns
Chip Enable to End of Write
t
ELWH
t
ELEH
t
CW
t
CW
8
8
9
9
10
10
15
15
20
20
ns
ns
Address Setup Time
t
AVWL
t
AVEL
t
AS
t
AS
0
0
0
0
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
t
AVWH
t
AVEH
t
AW
t
AW
9
9
10
10
12
12
15
15
15
15
ns
ns
Write Pulse Width
t
WLWH
t
WLEH
t
WP
t
WP
9
9
10
10
12
12
15
15
15
15
ns
ns
Write Recovery Time
t
WHAX
t
EHAX
t
WR
t
WR
0
0
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time
t
WHDX
t
EHDX
t
DH
t
DH
0
0
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
5
0
6
0
7
0
7
0
10
ns
Data to Write Time
t
DVWH
t
DVEH
t
DW
t
DW
5
5
6
6
8
8
8
8
12
12
ns
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
2
2
2
2
2
ns
AC CHARACTERISTICS - WRITE CYCLE
NOTE: Parameter guaranteed, but not tested.
A
E#
W#
D
Q
t
AVAV
t
AVEH
t
ELEH
t
WLEH
t
EHAX
HIGH Z
DATA VALID
t
DVEH
t
EHDX
t
AVEL
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32128C
August, 2002
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Part Number
Speed
(ns)
Package
No.
EDI8L32128C12AC
12
99
EDI8L32128C15AC
15
99
EDI8L32128C17AC
17
99
EDI8L32128C20AC
20
99
EDI8L32128C25AC
25
99
ORDERING INFORMATION
Part Number
Speed
(ns)
Package
No.
EDI8L32128C15AI
15
99
EDI8L32128C17AI
17
99
EDI8L32128C20AI
20
99
0.995
Max
0.956
Max
0.995
Max
0.956
Max
0.040
Max
0.020
0.015
0.930
0.890
0.050
BSC
0.115
Max
0.180
Max
PACKAGE DESCRIPTION
Package No. 99: 68 LEAD PLCC
JEDEC MO-47AE
ALL DIMENSIONS ARE IN INCHES
Commercial (0C to +70C)
Industrial (-40C to +85C)
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