1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32512C
August 2000
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
512Kx32 CMOS High Speed Static RAM
DESCRIPTION
The EDI8L32512C is a high speed, 5V, 16Mb SRAM. The
device is available with access times of 12, 15, 17 and
20ns allowing the creation of a no wait state DSP memory
solution. The high speed, 5v supply voltage and control lines
make the divice ideal for creating fl oating point DSP memory
solutions.
The device can be confi gured as a 512K x 32 and used to
create a single chip external data memory solution for TI's
TMS320C30/C31 (Figure 8), TMS320C32 (Figure 9) or
TMS320C4x (Figure 10), Motorola's DSP96002 and Analog's
SHARC DSP (Figure 11). Alternatively, the device's chip
enables can be used to confi gure it as a 1M x 16. A 1M x 48
program memory array for Analog's SHARC DSP is created
using three devices (Figure 12). If this memory is too deep,
two 512K x 24s (EDI8L24512C) can be used to create a 512K
x 48 array or two 128K x 48 array.
The device provides a 56% space savings when compared
to four 512K x 8, 36 pin SOJs. In addition the EDI8L32512C
has only a 10pF load on the data lines vs. 32pF for four
plastic SOJs.
The device provides a memory upgrade of the EDI8L32256C
(256K x 32) or the EDI8L32128C (128K x 32). For additional
upgrade information see Figure 13.
Note: Solder Refl ow Temperature should not exceed 230C for 10 seconds.
FEATURES
DSP Memory Solution
Motorola DSP96002
Analog SHARC DSP
Texas Instruments TMS320C3x, TMS320C4x
Random Access Memory Array
Fast Access Times: 12*, 15, 17, and 20ns
TTL Compatible I/O
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 JEDEC M0-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise Immunity
Single +5V (5%) Supply Operation
* Advanced Information
PIN NAMES
A0-A18
Address Inputs
E0#-E3#
Chip Enables
W#
Write Enables
G#
Output Enable
DQ0-DQ31
Common Data Input/Output
V
CC
Power (+5V 10%)
V
SS
Ground
NC
No Connection
FIG. 1 PIN CONFIGURATIONS AND BLOCK DIAGRAM
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
DQ24
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
V
CC
DQ7
DQ6
DQ5
DQ4
V
SS
DQ3
DQ2
DQ1
DQ31
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A6
A5
A4
A3
A2
A1
A0
V
CC
A13
A12
A1
1
A10
A9
A8
A7
DQ0
9
DQ16
8
A18
7
A17
6
E3#
5
E2#
4
E1#
3
E0#
2N
C
1
VCC
68
NC
67
NC
66
G#
65
W#
64
A16
63
A15
62
A14
61
DQ15
A0-18
G#
W#
E0#
E1#
E2#
E3#
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
512K x 32
Memory
Array
19
BYTE CONTROL
TABLE
Chip
Enable
Byte
Control
E0#
DQ0-7
E1#
DQ8-15
E2#
DQ16-23
E3#
DQ24-31
Note: For memory upgrade information, refer to Pg 8, Fig 13 "EDI MCM-L Upgrade Path"
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32512C
August 2000
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
CAPACITANCE
(f=1.0MHz, V
IN
=V
CC
or V
SS
)
AC TEST CONDITIONS
Note: For t
EHQZ
,t
GHQZ
and t
WLQZ
, CL = 5pF)
TRUTH TABLE
*Stress greater than those listed under "Ab so lute Maxi mum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional op era tion of the device at these or any other
conditions greater than those in di cated in the operational sections of
this speci fi ca tion is not im plied. Ex po sure to ab so lute maxi mum rating
con di tions for ex tended periods may affect re lia bil ity.
Voltage on any pin relative to V
SS
-0.5V to 7.0V
Operating Temperature t
A
(Ambient)
Commercial
Industrial
0C to +70C
-40C to +85C
Storage Temperature, Plastic
-55C to +125C
Power Dissipation
5.0 Watts
Output Current
20 mA
Junction Temperature, TJ
175C
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 2
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
4.75
5.0
5.25
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
V
CC
+0.5V
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
Parameter
Sym
Conditions
Min
Max
Units
ns
12-25
17/20
Operating Power Supply Current
I
CC1
W# = V
IL
, I
I/O
= 0mA, Min Cycle
800
720
mA
Standby (TTL) Power Supply Current
I
CC2
E# V
IH
, V
IN
V
IL
or V
IN
V
IH
, f = 0MHz
200
200
mA
Full Standby Power Supply Current
CMOS
I
CC3
E# V
CC
-0.2V
V
IN
V
CC
-0.2V or V
IN
0.2V
40
40
mA
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
10
A
Output Leakage Current
I
LO
V I/O = 0V to V
CC
10
A
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 8.0mA
0.4
V
G#
E#
W#
Mode
Output
Power
X
H
X
Standby
HIGH Z
I
CC2
I
CC3
H
L
H
Output Deselect
HIGH Z
I
CC1
L
L
H
Read
D
OUT
I
CC1
X
L
L
Write
D
IN
I
CC1
Parameter
Sym
Max
Unit
Address Lines
CI
30
pF
Data Lines
CD/Q
10
pF
Write & Output Enable Line
W#, G#
30
pF
Chip Enable Line
E0#-E3#
8
pF
FIG. 2
FIG. 3
30pF
480
Vcc
Q
255
5pF
480
Vcc
Q
255
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32512C
August 2000
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS READ CYCLE
READ CYCLE 2 - W# HIGH
*Advanced Information
Note: 1. Parameter guaranteed, but not tested.
READ CYCLE 1 - W# HIGH, G#, E# LOW
FIG. 5
FIG. 4
Parameter
Symbol
12ns*
15ns
17ns
20ns
Units
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
12
15
17
20
ns
Address Access Time
t
AVQV
t
AA
12
15
17
20
ns
Chip Enable Access
t
ELQV
t
ACS
12
15
17
20
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
3
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
6
7
9
9
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
6
7
9
9
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
0
ns
Output Disable to Output in High Z (1)
t
GHQZ
t
OHZ
6
7
9
9
ns
ADDRESS 1
ADDRESS 2
t
AVAV
DATA 1
DATA 2
t
AVQV
t
AVQX
A
Q
t
GHQZ
t
ELQV
t
ELQX
E#
G#
Q
t
EHQZ
A
t
AVAV
t
GLQV
t
GLQX
t
AVQV
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32512C
August 2000
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
*Advanced Information.
Note 1: Parameter guaranteed, but not tested.
AC CHARACTERISTICS WRITE CYCLE
Parameter
Symbol
12ns
15ns
17ns
20ns
Units
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
WC
12
15
17
20
ns
Chip Enable to End of Write
t
ELWH
t
ELEH
t
CW
t
CW
8
8
10
10
11
11
12
12
ns
ns
Address Setup Time
t
AVWL
t
AVEL
t
AS
t
AS
0
0
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
t
AVWH
t
AVEH
t
AW
t
AW
8
8
10
10
11
11
12
12
ns
ns
Write Pulse Width
t
WLWH
t
ELEH
t
WP
t
WP
8
10
10
12
11
13
12
14
ns
ns
Write Recovery Time
t
WHAX
t
EHAX
t
WR
t
WR
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time
t
WHDX
t
EHDX
t
DH
t
DH
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
6
0
7
0
8
0
9
ns
Data to Write Time
t
DVWH
t
DVEH
t
DW
t
DW
6
6
7
7
8
8
9
9
ns
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
3
3
3
3
ns
WRITE CYCLE 1 - W# CONTROLLED
FIG. 6
E#
A
t
AVAV
t
ELWH
t
AVWH
t
WLWH
t
AVWL
t
WHAX
W#
HIGH Z
DATA VALID
t
WLQZ
t
WHQX
t
DVWH
t
WHDX
Q
D
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI8L32512C
August 2000
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
WRITE CYCLE 2 - E# CON TROLLED
FIG. 7
A
t
AVEL
HIGH Z
t
AVAV
t
ELEH
E
t
AVEH
t
EHAX
W#
t
WLEH
t
EHDX
t
DVEH
Q
DATA VALID
D
Commercial (0C to +70C)
ORDERING INFORMATION
Part Number
Speed
(ns)
Package
No.
EDI8L32512C12AC*
12
99
EDI8L32512C15AC
15
99
EDI8L32512C17AC
17
99
EDI8L32512C20AC
20
99
Industrial (-40C to +85C)
Part Number
Speed
(ns)
Package
No.
EDI8L32512C15AI*
15
99
EDI8L32512C17AI
17
99
EDI8L32512C20AI
20
99
PACKAGE DRAWING
Package No. 99
68 Lead PLCC
JEDEC MO-47AE
Weight = 4.2g
Theta J
A
= 40C/W
Theta J
C
= 15C/W
Package No. 99
68 lead PLCC
0.956
Max
0.995
Max
0.956
Max
0.995
Max
0.180
Max
0.115
Max
0.040
Max
0.050
BSC
0.020
0.015
0.930
0.890
Coplanarity (lowest lead to highest lead)0.004
PDF 
ZIP