ChipFind - документация

Электронный компонент: EDI9F416512C

Скачать:  PDF   ZIP
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI9F416512C
October 2001 Rev. 2
ECO #14609
4x512Kx16 Static RAM CMOS, Module
FEATURES
n
4x512Kx16 bit CMOS Static
n
Random Access Memory
Access Times 70 thru 100ns
Data Retention Function (EDI9F416512LP )
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n
High Density Packaging
80 Pin SIMM, No. 372
n
Single +5V (10%) Supply Operation
DESCRIPTION
FIG. 1:
P
IN
N
AMES
The EDI9F416512C is a 32Mb CMOS Static RAM based
on eight 512Kx8 Static RAMs mounted on a multi-lay-
ered epoxy laminate (FR-4) substrate.
A low power version with data retention
(EDI9F416512LP) is also available.
All inputs and outputs are TTL compatible and operate
from a single +5V supply. Fully asynchronous, the
EDI9F416512C requires no clocks or refreshing for
operation.
P
IN
C
ONFIGURATIONS
AND
B
LOCK
D
IAGRAM
A-A18
E
G
WH
WL
E
E1
E2
E3
128K
x 8
128K
x 8
128K
x 8
128K
x 8
128K
x 8
128K
x 8
128K
x 8
128K
x 8
DQ8-DQ15
DQ-DQ7
Vss
1
Vcc
2
NC 3
G 4
WH
5
WL 6
NC 7
E 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
NC 15
NC 16
NC 17
NC 18
NC 19
NC 20
E3 21
E2 22
E1 23
E0 24
Vss
25
NC 26
NC 27
NC 28
NC 29
NC 30
NC 31
NC 32
NC 33

A18 34

A17 35

A16 36

A15 37

A14 38

A13 39

A12 40
A11 41
A10 42
A9 43
A8 44
A7 45
A6 46
A5 47
A4 48
A3 49
A2 50
A1 51
A0 52
Vss
53
Vss
54
DQ15
55
DQ14
56
DQ13
57
DQ12
58
DQ11
59
DQ10
60
DQ9 61
DQ8 62
DQ7 63
DQ6 64
DQ5 65
DQ4 66
DQ3 67
DQ2 68
DQ1 69
DQ
70
NC 71
Vcc
72
NC 73
Vss
74
NC 75
Vss
76
Vss
77
NC 78
NC 79
Vss
80
A-A18
Address Inputs
E-E3
Chip Enable
G
Output Enables
WH-WL
Write Enables
E
Chip Select
DQ-DQ15
Data Input/Output
VCC
Supply 5 Volts
VSS
Ground
NC
No Connect
2
White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
EDI9F416512C
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
*Stress greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may
affect reliability.
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Industrial
-40C to +85C
Storage Temperature
Plastic
-55C to +125C
Power Dissipation
1 Watt
Output Current
20 mA
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
AC T
EST
C
ONDITIONS
(NOTE: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage VIH
2.2
6.0
V
Input Low Voltage
VIL
-0.3
0.8
V
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
70ns
1TTL = 30pF
85-120ns
1TTL, CL =100pF
DC E
LECTRICAL
C
HARACTERISTICS
T
RUTH
T
ABLE
C
APACITANCE
(
F
=1.0MH
Z
, VIN=VCC
OR
VSS)
Parameter
Sym
Conditions
Min
Typ
Max
Units
Operating Power
ICC1
W, E = VIL, II/O = 0mA,
100
158
mA
Supply Current
Min Cycle
Standby (TTL) Power
ICC2
E VIH, VIN VIL
5
35
mA
Supply Current
VIN VIH
Full Standby Power
ICC3
E VCC-0.2V
C
25
mA
Supply Current
VIN VCC-0.2V or
LP
150
A
CMOS
VIN 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
10
A
Output Leakage Current
ILO
V I/O = 0V to VCC
10
A
Output High Voltage
VOH
IOH = -1.0mA
2.4
V
Output Low Voltage
VOL
IOL = 2.1mA
0.4
V
G
E
W
Mode
Output
Power
X
H
X
Standby
High Z
ICC2, ICC3
H
L
H
Output Deselect
High Z
ICC1
L
L
H
Read
DOUT
ICC1
X
L
L
Write
DIN
ICC1
Parameter
Sym
Max
Unit
Address Lines
CI
60
pF
Data Lines
CD/Q50
pF
Chip Enable Line
CC
25
pF
Write and Output Enable Lines
CW
60
pF
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI9F416512C
AC C
HARACTERISTICS
R
EAD
C
YCLE
FIG. 2 READ CYCLE 1 - W HIGH, G, E LOW
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
TAVAV
TRC
70
85
100
ns
Address Access Time
TAVQV
TAA
70
85
100
ns
Chip Enable Access Time
TELQV
TACS
70
85
100
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
5
5
5
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
30
35
40
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
40
45
50
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
0
0
0
ns
Output Disable to Output in High Z(1)
TGHQZ
TOHZ
30
35
40
ns
FIG. 3 READ CYCLE 2 - W HIGH
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
9F416128C Rd Cyc1
A
Q
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
9F416128C Rd Cyc2
4
White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
EDI9F416512C
AC C
HARACTERISTICS
W
RITE
C
YCLE
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
TAVAV
TWC
70
85
100
ns
Chip Enable to End of Write
TELWH
TCW
65
70
80
ns
TELEH
TCW
65
70
80
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
65
70
80
ns
TAVEH
TAW
65
70
80
ns
Write Pulse Width
TWLWH
TWP
65
70
80
ns
TWLEH
TWP
65
70
80
ns
Write Recovery Time
TWHAX
TWR
0
0
0
ns
TEHAX
TWR
0
0
0
ns
Data Hold Time
TWHDX
TDH
0
0
0
ns
TEHDX
TDH
0
0
0
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
30
0
35
0
40
ns
Data to Write Time
TDVWH
TDW
30
35
40
ns
TDVEH
TDW
30
35
40
ns
Output Active from End of Write (1)
TWHQX
TWLZ
5
5
5
ns
FIG. 4 WRITE CYCLE 1 - W CONTROLLED
Note 1: Parameter guaranteed, but not tested. *Advance Information
E
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
9F416128C Write Cyc1
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI9F416512C
FIG. 5 WRITE CYCLE 2 - E CONTROLLED
D
ATA
R
ETENTION
C
HARACTERISTICS
Characteristic
Sym
Test Conditions
VDD
Min
Typ
Max
Unit
Data Retention Voltage
VDD
VDD = 0.2V
2
V
Data Retention Quiescent Current
ICCDR
E VDD -0.2V
A
VIN VDD -0.2V
3V
8
100
A
Chip Disable to Data Retention Time(1)
TCDR
or VIN 0.2V
0
ns
Operation Recovery Time (1)
TR
5
ms
FIG. 6 DATA RETENTION - E CONTROLLED
VCC
TR
9F416128C Data Retent.
DATA RETENTION MODE
E
TCDR
E
VDD-0.2V
VDD
4.5V
4.5V
A
TAVEL
HIGH Z
TAVAV
9F416128C Write Cyc2
TELEH
E
TAVEH
TEHAX
W
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D