White Electronic Designs Corporation (508) 366-5151

www.whiteedc.com

W2Z1M72SJ

DESCRIPTION

The WEDC SyncBurst - SRAM family employs high-

speed, low-power CMOS designs that are fabricated us-

ing an advanced CMOS process. WEDCs 72Mb

SyncBurst SRAMs integrate two 1Mx36 SRAMs into a

single BGA package to provide a 1Mx72 configuration.

All synchronous inputs pass through registers controlled

by a positive-edge-triggered single-clock input (CLK).

The NBL or No Bus Latency Memory utilizes all the band-

width in any combination of operating cycles. Address,

data inputs, and all control signals except output enable

and linear burst order are synchronized to input clock.

Burst order control must be tied High or Low. Asyn-

chronous inputs include the sleep mode enable (ZZ) and

Output Enable (OE). Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This

feature eliminates complex off-chip write pulse genera-

tion and provides increased timing flexibility for incom-

ing signals.

72Mb, 1Mx72 Synchronous Pipeline Burst NBL SRAM

FIG. 1 PIN CONFIGURATION

BLOCK DIAGRAM

(TOP VIEW)

Address Bus

)

- D

1M x 36

CLK
CKE
ADV
LBO
CS

OE
WE
BW

CLK
CKE

ADV

LBO

CLK
CKE
ADV
LBO
CS

OE
WE

FEATURES

Fast clock speed: 225, 200, 166 and 150MHz

Fast access times: 2.8, 3.0, 3.5 and 3.8ns

Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns

Separate Core and I/O Power Supply

Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses,
data I/Os and control signals

Burst control (interleaved or linear burst)

Packaging:
209-bump BGA package, JEDEC Pin Definition

Low capacitive bus loading

Preliminary*

* This data sheet describes a product that may not be fully qualified or

characterized and is subject to change without notice.

A DQ

ADV

B DQ

C DQ

NC CS

NC BW

D DQ

E DQP

DQP

DDQ

DQP

F DQ

G DQ

DDQ

H DQ

DDQ

CLK

CKE

L DQ

DDQ

M DQ

N DQ

DDQ

P DQ

R DQP

DQP

DDQ

DQP

T DQ

NC LBO

U DQ

NC DQ

V DQ

W DQ

RFU RFU

RFU RFU DQ

January 2003 Rev. 1

ECO #15889

White Electronic Designs Corporation Westborough, MA (508) 366-

5151

W2Z1M72SJ

BURST SEQUENCE TABLE

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

(Interleaved Burst, LBO = High)

Case 1

Case 2

Case 3

Case 4

LBO PinHigh

First Address

Fourth Address

(Linear Burst, LBO = Low)

Case 1

Case 2

Case 3

Case 4

LBO PinHigh

First Address

Fourth Address

FUNCTION DESCRIPTION

The W2Z1M72SJ is an NBL SSRAM designed to sus-

tain 100% bus bandwidth by eliminating turnaround

cycle when there is transition from Read to Write, or

vice versa. All inputs (with the exception of OE, LBO

and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the

ADV input. Subsequent burst addresses can be inter-

nally generated by the burst advance pin (ADV). ADV

should be driven to Low once the device has been de-

selected in order to load a new address for next opera-

tion.
Clock Enable (CKE) pin allows the operation of the chip

to be suspended as long as necessary. When CKE is

high, all synchronous inputs are ignored and the inter-

nal device registers will hold their previous values. NBL

SSRAM latches external address and initiates a cycle

when CKE and ADV are driven low at the rising edge of

the clock.
Output Enable (OE) can be used to disable the output

at any given time. Read operation is initiated when at

the rising edge of the clock, the address presented to

the address inputs are latched in the address register,

CKE is driven low, the write enable input signals WE

are driven high, and ADV driven low. The internal array

is read between the first rising edge and the second

rising edge of the clock and the data is latched in the

output register. At the second clock edge the data is

driven out of the SRAM. During read operation OE must

be driven low for the device to drive out the requested

data.

Write operation occurs when WE is driven low at the

rising edge of the clock. BW[d:a] can be used for byte

write operation. The pipe-lined NBL SSRAM uses a late-

late write cycle to utilize 100% of the bandwidth. At the

first rising edge of the clock, WE and address are reg-

istered, and the data associated with that address is

required two cycle later.
Subsequent addresses are generated by ADV High for

the burst access as shown below. The starting point of

the burst seguence is provided by the external address.

The burst address counter wraps around to its initial

state upon completion. The burst sequence is deter-

mined by the state of the LBO pin. When this pin is low,

linear burst sequence is selected. And when this pin is

high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When

ZZ is driven high, the SRAM will enter a Power Sleep

Mode after 2 cycles. At this time, internal state of the

SRAM is preserved. When ZZ returns to low, the SRAM

operates after 2 cycles of wake up time.

White Electronic Designs Corporation (508) 366-5151

www.whiteedc.com

W2Z1M72SJ

TRUTH TABLES

YNCHRONOUS

RUTH

ABLE

RITE

RUTH

ABLE

BWa

BWb

BWc

BWd

Operation

XXXX

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

NOTES:

1. X means Dont Care.

2. All inputs in this table must meet setup and hold time around the rising edge of

CLK (�).

CEx

ADV

BWx

CKE

CLK

Address Accessed

Operation

�

N/A

Deselect

�

N/A

Continue Deselect

�

External Address

Begin Burst Read Cycle

�

Next Address

Continue Burst Read Cycle

�

External Address

NOP/Dummy Read

�

Next Address

Dummy Read

�

External Address

Begin Burst Write Cycle

�

Next Address

Continue Burst Write Cycle

�

N/A

NOP/Write Abort

�

Next Address

Write Abort

�

Current Address

Ignore Clock

NOTES:

1. X means Dont Care.

2. The rising edge of clock is symbolized by (�)

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins (ZZ and OE).

6. CEx refers to the combination of CE1, CE2 and CE2.

White Electronic Designs Corporation Westborough, MA (508) 366-

5151

W2Z1M72SJ

BSOLUTE

AXIMUM

ATINGS

Voltage on V

Supply Relative to V

-0.3V to +3.6V

(DQx)

-0.3V to +3.6V

(Inputs)

-0.3V to +3.6V

Storage Temperature (BGA)

-55�C to +125�C

Short Circuit Output Current

100mA

LECTRICAL

HARACTERISTICS

*Stress greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions greater than those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating condtions for extended periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

1.7

+0.3

Input Low (Logic 0) Voltage

-0.3

0.7

Input Leakage Current

0V � V

� V

-5

�A

Output Leakage Current

Output(s) Disabled, 0V � V

� V

-5

�A

Output High Voltage

= -1.0mA

2.0

Output Low Voltage

= 1.0mA

0.4

Supply Voltage

2.375

2.625

NOTES:

1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage is higher.

DC C

HARACTERISTICS

NOTES:

1. IDD is specified with no output current and increases with faster cycle times.

2. Typical values are measured at 2.5V, 25�C, and 10ns cycle time.

3. Typical values are measured at 2.5V, 25�C.

BGA C

APACITANCE

NOTES:

1. This parameter is sampled.

Description

Symbol

Conditions

Typ

Max

Units

Notes

Control Input Capacitance

= 25�C; f = 1MHz

Input/Output Capacitance (DQ)

= 25�C; f = 1MHz

Address Capacitance

= 25�C; f = 1MHz

Clock Capacitance

= 25�C; f = 1MHz

225

200

166

150

Description

Symbol

Conditions

Typ

MHz MHz MHz MHz

Units

Notes

Power Supply

Device Selected; All Inputs � V

or � V

; Cycle

865

800

745

690

1, 2

Current: Operating

Time = t

CYC

MIN; V

= MAX; Output Open

Power Supply

SB2

Device Deselected; V

= MAX; All Inputs � V

+ 0.2

Current: Standby

or V

- 0.2; All Inputs Static; CLK Frequency = 0;

ZZ � V

Power Supply

SB3

Device Selected; All Inputs � V

or � V

; Cycle

Current: Current

Time = t

CYC

MIN; V

= MAX; Output Open;

ZZ � V

- 0.2V

Clock Running

SB4

Device Deselected; V

= MAX; All Inputs

170

160

150

135

Standby Current

� V

+ 0.2 or V

- 0.2; Cycle Time = t

CYC

MIN; ZZ � V

White Electronic Designs Corporation (508) 366-5151

www.whiteedc.com

W2Z1M72SJ

AC C

HARACTERISTICS

NOTES:

1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is

sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.

3. A WRITE cycle is defined by WE low having been registered into the device at ADV Low.

A READ cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times.

UTPUT

OAD

(A)

UTPUT

OAD

(B)

(

FOR

LZC

, t

LZOE

, t

HZOE

AND

HZC

)

Symbol

225MHz

200MHz

166MHz

150MHz

Parameter

MinMax

its

Clock Time

CYC

4.4

5.0

6.0

6.7

Clock Access Time

2.8

3.0

3.5

3.8

Output enable to Data Valid

2.8

3.0

3.5

3.8

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

2.5

3.0

Clock High to Output High-Z

HZC

2.5

3.0

Clock High Pulse Width

1.8

2.0

2.2

2.5

Clock Low Pulse Width

1.8

2.0

2.2

2.5

Address Setup to Clock High

1.5

CKE Setup to Clock High

CES

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

1.5

Address Advance to Clock High

ADVS

1.5

Chip Select Setup to Clock High

CSS

1.5

Address Hold to Clock high

0.5

CKE Hold to Clock High

CEH

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

0.5

Address Advance to Clock High

ADVH

0.5

Chip Select Hold to Clock High

CSH

0.5

Dout

Zo=50

RL=50

VL=1.25V

30pF*

Dout

1538

5pF*

+2.5V

1667

*Including Scope and Jig Capacitance

AC T

EST

ONDITIONS

= 2.5V � 5%, U

NLESS

THERWISE

PECIFIED

)

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A)

White Electronic Designs Corporation Westborough, MA (508) 366-

5151

W2Z1M72SJ

SNOOZE MODE

SNOOZE MODE is a low-current, power-down mode

in which the device is deselected and current is reduced

to I

. The duration of SNOOZE MODE is dictated by

the length of time Z is in a HIGH state. After the device

enters SNOOZE MODE, all inputs except ZZ become

gated inputs and are ignored. ZZ is an asynchronous,

active HIGH input that causes the device to enter

SNOOZE MODE.

When ZZ becomes a logic HIGH, I

is guaranteed

after the setup time t

is met. Any READ or WRITE

operation pending when the device enters SNOOZE

MODE is not guaranteed to complete successfully.

Therefore, SNOOZE MODE must not be initiated until

valid pending operations are completed.

NOOZE

ODE

Description

Conditions

Symbol

Min

Max

Units

Notes

Current during SNOOZE MODE

ZZ � VIH

SB2Z

ZZ active to input ignored

2(t

)

ZZ inactive to input sampled

RZZ

2(t

)

ZZ active to snooze current

ZZI

2(t

)

ZZ inactive to exit snooze current

RZZI

FIG. 2 SNOOZE MODE TIMING DIAGRAM

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

White Electronic Designs Corporation Westborough, MA (508) 366-

5151

W2Z1M72SJ

PACKAGE DIMENSION: 209 BUMP PBGA

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

2.50 (0.099)

MAX

0.600 (0.024)

MAX

1.27 (0.050)

TYP

1.00 TYP

14.00 (0.551) TYP

A1
CORNER

18.00

TYP

22.00 (0.866)

TYP

10.00 (0.394)

TYP

R 1.52 (0.060)

MAX (4x)

11 10

ORDERING INFORMATION

Commercial Temp Range (0�C to 70�C), Industrial Temp. Range (-40� to 85�C)
Part Number

Configuration

Clock

Operating

(ns)

(MHz)

Range

W2Z1M72SJ35ES

1M x 72

3.5

166

Engineering Samples

W2Z1M72SJ38ES

1M x 72

3.8

150

Engineering Samples

W2Z1M72SJ28BC

1M x 72

2.8

225

Commercial

W2Z1M72SJ30BC

1M x 72

3.0

200

Commercial

W2Z1M72SJ35BC

1M x 72

3.5

166

Commercial

W2Z1M72SJ38BC

1M x 72

3.8

150

Commercial

W2Z1M72SJ30BI

1M x 72

3.0

200

Industrial

W2Z1M72SJ35BI

1M x 72

3.5

166

Industrial

W2Z1M72SJ38BI

1M x 72

3.8

150

Industrial

NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.

Электронный компонент: W2Z1M72SJ-XBX