1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dy nam ic ran dom-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally confi gured as a
quad-bank DRAM with a syn chro nous interface. Each of
the chip's 134,217,728-bit banks is or ga nized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; ac cess es start at a selected location and continue
for a pro grammed number of locations in a programmed
se quence. Ac cess es be gin with the registration of an
ACTIVE com mand, which is then fol lowed by a READ or
WRITE com mand. The address bits reg is tered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits reg is tered co in ci dent
with the READ or WRITE com mand are used to se lect the
starting col umn lo ca tion for the burst ac cess.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be en abled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is com pat i ble
with the 2n rule of prefetch architectures, but it also allows
the column ad dress to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while ac cess ing one of the other three banks
will hide the precharge cycles and provide seam less, high-
speed, random-access op er a tion.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
32Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
208 Plastic Ball Grid Array (PBGA), 16 x 22mm
3.3V 0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on pos i tive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8192 refresh cycles
Commercial, Industrial and Military Temperature
Rang es
Organized as 32M x 72
Weight: W332M72V-XSBX - 2.0 grams typical
BENEFITS
73% SPACE SAV INGS
Re duced part count
Re duced I/O count
23% I/O Re duc tion
Re duced trace lengths for low er par a sit ic
ca pac i tance
Suitable for hi-re li abil i ty ap pli ca tions
Lami nate in ter pos er for op ti mum TCE match
* This product is subject to change without notice.
Discrete Approach
ACTUAL SIZE
S
A
V
I
N
G
S
Area
5 x 265mm
2
= 1325mm
2
352mm
2
73%
I/O
5 x 54 pins = 270 pins
208 Balls
23%
Count
16
22
11.9 11.9 11.9 11.9 11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
W332M72V-XSBX
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
FIGURE 1 PIN CONFIGURATION
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally
Ball J10 is NC on this device; will be used as A13 for future density upgrades.
Top View
1 2 3 4 5 6 7 8 9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
SS
CS2# CS0# CKE2 CKE0 CAS2# RAS0# RAS2# V
SS
V
CCQ
V
SS
NC NC CLK0 CLK2
DQML0
DQML2
CAS0#
WE0#
WE2# V
SS
DQMH2
DQMH0 NC NC DQ8 DQ40 DQ5 DQ39 DQ7 NC NC
DQ41 DQ9 DQ10 DQ42 DQ43 DQ12 DQ3 DQ36 DQ4 DQ38 DQ6
DQ44 DQ11 DQ13 DQ45 DQ14 DQ33 DQ1 DQ34 DQ2 DQ37 DQ35
DQ64 DQ65 DQ15 DQ47 DQ46 V
SS
DQ32 DQ0 DQ77 DQ79 DQ78
DNU DQ66 DQ69 DNU DQ67 V
CC
DQ72 DQ73 DQ74 DQ75 DQ76
V
CCQ
A12 BA1 A0 V
CC
V
SS
V
CCQ
A7 A9 NC(A13)
V
CC
V
SS
A10 A3 V
CCQ
V
SS
NC V
SS
V
CCQ
A4 A11 V
SS
V
CC
A2 BA0 A1 V
CCQ
V
SS
V
CC
A6 A8 A5 V
CCQ
DQ71
DQ70
NC
DQML4 DQ68
V
CC
NC DQMH4 NC CLK4 DNU
WE4# CAS4# RAS4# DQ16
DQ48
V
SS
DQ63 DQ31 DQ62 CKE4 CS4#
DQ22 DQ52 DQ18 DQ50 DQ17 DQ49 DQ30 DQ61 DQ29 DQ59 DQ27
DQ23 DQ54 DQ21 DQ19 DQ51 DQ60 DQ28 DQ58 DQ26 DQ57 DQ25
NC NC DQ55 DQ53 DQ20 DQ56 DQ24 DQMH3
DQMH1 NC NC
V
SS
CAS3# WE3# WE1# DQML3
DQML1 NC NC CLK1 CLK3 V
SS
V
CCQ
V
SS
CAS1# RAS3# RAS1# CKE1 CKE3 CS1# CS3# V
SS
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
Register Defi nition
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode
of op er a tion of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an op er at ing mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REG IS TER command and will retain the stored
in for ma tion until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
spec i fi es the type of burst (sequential or in ter leaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
op er at ing mode, M9 spec i fi es the WRITE burst mode,
and M10 and M11 are reserved for future use. Address
A12 (M12) is undefi ned but should be driven LOW during
loading of the mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
ini ti at ing the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
Fig ure 3. The burst length determines the maximum
number of column lo ca tions that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are avail able for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown op er a tion
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
col umns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
mean ing that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-9 when the burst length is set to two; by A2-9 when
the burst length is set to four; and by A3-9 when the burst
length is set to eight. The remaining (least signifi cant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached
All inputs and outputs are LVTTL compatible. SDRAMs offer
sub stan tial ad vanc es in DRAM op er at ing per for mance,
in clud ing the ability to syn chro nous ly burst data at a high
data rate with au to mat ic column-ad dress gen er a tion,
the ability to in ter leave be tween in ter nal banks in order
to hide precharge time and the capability to ran dom ly
change col umn ad dress es on each clock cy cle dur ing a
burst ac cess.
FUNCTIONAL DE SCRIP TION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
pro grammed number of locations in a pro grammed
se quence. Ac cess es begin with the registration of an
ACTIVE com mand which is then followed by a READ or
WRITE com mand. The address bits registered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-9) reg is tered
coincident with the READ or WRITE com mand are used to
select the start ing column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
cov er ing device initialization, register defi nition, command
de scrip tions and de vice operation.
Initialization
SDRAMs must be pow ered up and initialized in a pre defi ned
manner. Operational pro ce dures other than those spec i fi ed
may result in undefi ned operation. Once power is ap plied
to V
CC
and V
CCQ
(si mul ta neous ly) and the clock is stable
(stable clock is de fi ned as a signal cycling within tim ing
constraints specified for the clock pin), the SDRAM
re quires a 100s delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100s period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP com mands should be applied.
Once the 100s delay has been satisfi ed with at least
one COM MAND INHIBIT or NOP command having been
ap plied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
per formed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming. Be cause
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
TABLE 1 BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = In ter leaved
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A
0
-9
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
Not Supported
FIGURE 3 MODE REGISTER DEFINITION
NOTES:
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A
10
A
11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
A
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