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January 2005
Rev. 1

W364M72V-XSBX

ADVANCED*

Discrete Approach

SAVINGS Area: 66% I/O Count: 55%

Area = 800mm

Area: 9 x 265mm

= 2,385mm

I/O Count = 219 Balls

I/O Count: 9 x 54 pins = 486 pins

11.9

22.3

TSOP

ACTUAL SIZE

White Electronic Designs

W364M72V-XSBX

BENEFITS

66% SPACE SAVINGS

Reduced part count from 9 to 1

Reduced I/O count
· 55% I/O Reduction

Reduced trace lengths for lower parasitic
capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

GENERAL DESCRIPTION

The 512MByte (4.5Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
512M bits. Each chip is internally confi gured as a quad-
bank DRAM with a synchronous interface. Each of the
chip's 134,217,728-bit banks is organized as 8,192 rows
by 2,048 columns by 8 bits.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a

64Mx72 Synchronous DRAM

FEATURES

High Frequency = 100, 125MHz

Package:
· 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

3.3V ±0.3V power supply for core and I/Os

Fully Synchronous; all signals registered on positive
edge of system clock cycle

Internal pipelined operation; column address can be
changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature
Ranges

Organized as 64M x 72

Weight: W364M72V-XSBX - TBD grams typical

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

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January 2005
Rev. 1

W364M72V-XSBX

ADVANCED

programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select
the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.

The 4.5Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.

The 4.5Gb SDRAM is designed to operate at 3.3V. An
auto refresh mode is provided, along with a power-saving,
power-down mode.

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White Electronic Designs

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W364M72V-XSBX

ADVANCED

FIGURE 1 PIN CONFIGURATION

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.

NC = Not Connected Internally.

Top View

CAS

Vss

CLK

CKE

CAS

DQML0

RAS

CKE

CLK

DQMH3

DQMH1

CCQ

RAS

DQML2

Vss

DQMH0

CLK

CKE

CCQ

CAS

DQML1

CKE

CLK

DQMH2

CCQ

RAS

DQML3

CCQ

RAS

CAS

DNU

CLK

DNU

CAS

CCQ

CKE

CCQ

RAS

DQML4

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White Electronic Designs

January 2005
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W364M72V-XSBX

ADVANCED

FIGURE 2 FUNCTIONAL BLOCK DIAGRAM

0-12

0-1

CLK

CKE

DQML

IC1

0-12

0-1

CLK

IC0

CKE

DQML

DQM

IC2

0-12

0-1

CLK

CKE

DQML

DQM

IC3

0-12

0-1

CLK

CKE

DQML

DQM

IC4

0-12

0-1

CLK

CKE

DQML

DQM

CLK

CKE

DQMH

CS#

RAS

CAS

WE# RAS# CAS#

CS#

CLK

CKE

DQMH

DQM

CS#

RAS

CAS

WE# RAS# CAS#

CS#

CLK

CKE

DQMH

DQM

CS#

RAS

CAS

WE# RAS# CAS#

CS#

CLK

CKE

DQMH

DQM

CS#

RAS

CAS

WE# RAS# CAS#

CS#

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQM

IC6

0-12

0-1

IC5

IC7

0-12

0-1

IC8

0-12

0-1

CS#

WE# RAS# CAS#

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REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to defi ne the specifi c mode
of op er a tion of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an op er at ing mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REG IS TER command and will retain the stored
in for ma tion until it is programmed again or the device
loses power.

Mode register bits M0-M2 specify the burst length, M3
spec i fi es the type of burst (sequential or in ter leaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
op er at ing mode, M9 spec i fi es the WRITE burst mode,
and M10 and M11 are reserved for future use. Address
A12 (M12) is undefi ned but should be driven LOW during
loading of the mode register.

The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
ini ti at ing the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.

BURST LENGTH

Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Fig ure 3. The burst length determines the maximum
number of column lo ca tions that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are avail able for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.

Reserved states should not be used, as unknown op er a tion
or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
col umns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
mean ing that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-9, A11 when the burst length is set to two; by A2-9,
A11 when the burst length is set to four; and by A3-9, A11
when the burst length is set to eight. The remaining (least
signifi cant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within the
page if the boundary is reached.

All inputs and outputs are LVTTL compatible. SDRAMs offer
sub stan tial ad vanc es in DRAM op er at ing per for mance,
in clud ing the ability to syn chro nous ly burst data at a high
data rate with au to mat ic column-ad dress gen er a tion,
the ability to in ter leave be tween in ter nal banks in order
to hide precharge time and the capability to ran dom ly
change col umn ad dress es on each clock cy cle dur ing a
burst ac cess.

FUNCTIONAL DE SCRIP TION

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a pro grammed number of locations in a pro grammed
se quence. Ac cess es begin with the registration of an
ACTIVE com mand which is then followed by a READ or
WRITE com mand. The address bits registered coincident
with the AC TIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits (A0-9, A11) reg is tered
coincident with the READ or WRITE com mand are used to
select the start ing column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
cov er ing device initialization, register defi nition, command
de scrip tions and de vice operation.

INITIALIZATION

SDRAMs must be pow ered up and initialized in a pre defi ned
manner. Operational pro ce dures other than those spec i fi ed
may result in undefi ned operation. Once power is ap plied
to V

and V

CCQ

(si mul ta neous ly) and the clock is stable

(stable clock is de fi ned as a signal cycling within tim ing
constraints specified for the clock pin), the SDRAM
re quires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP com mands should be applied.

Once the 100µs delay has been satisfi ed with at least
one COM MAND INHIBIT or NOP command having been
ap plied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be
per formed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming.
Be cause the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.

ADVANCED

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TABLE 1 BURST DEFINITION

Burst

Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential

Type = In ter leaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n = A

-9

(location 0-y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

...Cn - 1,

Cn...

Not Supported

FIGURE 3 MODE REGISTER DEFINITION

NOTES:
1. For full-page accesses: y = 2,048.
2. For a burst length of two, A1-9, A11 select the block-of-two burst; A0 selects the

starting column within the block.

3. For a burst length of four, A2-9, A11 select the block-of-four burst; A0-1 select the

starting column within the block.

4. For a burst length of eight, A3-9, A11 select the block-of-eight burst; A0-2 select the

starting column within the block.

5. For a full-page burst, the full row is selected and A0-9, A11 select the starting

column.

6. Whenever a boundary of the block is reached within a given sequence above, the

following access wraps within the block.

7. For a burst length of one, A0-9, A11 select the unique column to be accessed, and

Mode Register bit M3 is ignored.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = 0, 0

to ensure compatibility

with future devices.

ADVANCED

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FIGURE 4 CAS LATENCY

OPERATING MODE

The nor mal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are re served for future use and/or test modes. The
pro grammed burst length applies to both READ and
WRITE bursts.

Test modes and reserved states should not be used
be cause unknown operation or incompatibility with future
versions may result.

TABLE 2 CAS LATENCY

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

LATENCY = 2

CAS

LATENCY = 3

-100

100

-125

100

125

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.

CLK

Command

I/O

CLK

Command

I/O

T0 T1 T2 T3

T0 T1 T2 T3 T4

READ NOP NOP

CAS Latency = 2

OUT

READ NOP NOP NOP

OUT

CAS Latency = 3

DON'T CARE

UNDEFINED

BURST TYPE

Accesses within a given burst may be pro grammed to be
either se quen tial or interleaved; this is re ferred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is de ter mined by
the burst length, the burst type and the start ing column
address, as shown in Table 1.

CAS LATENCY

The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the avail abil i ty
of the fi rst piece of output data. The latency can be set to
two or three clocks.

If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock
edge one cycle ear li er (n + m - 1), and provided that the
rel e vant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is pro grammed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the op er at ing fre quen cies at which each CAS
latency setting can be used.

Reserved states should not be used as unknown op er a tion
or incompatibility with future versions may result.

ADVANCED

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TRUTH TABLE - COMMANDS AND DQM OPERATION (NOTE 1)

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

DQM

ADDR

I/Os

COMMAND

INHIBIT

(NOP)

H X X X X

NO OPERATION (NOP)

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

L/H

Bank/Col

Valid

BURST

TERMINATE

L H H L X

Active

PRECHARGE (Deactivate row in bank or banks) ( 5)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

Op-Code

Write Enable/Output Enable (8)

Active

Write Inhibit/Output High-Z (8)

High-Z

command can only be issued when all banks are idle, and
a sub se quent ex e cut able com mand cannot be issued until
t

MRD

is met.

ACTIVE

The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs se lects the bank, and the
address pro vid ed on inputs A0-12 selects the row. This row
remains active (or open) for ac cess es until a PRECHARGE
com mand is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.

READ

The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-9, A11
se lects the starting column location. The value on input
A10 de ter mines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent ac cess es. Read data appears
on the I/Os sub ject to the logic level on the DQM inputs

COMMANDS

The Truth Table provides a quick reference of available
com mands. This is followed by a written de scrip tion of each
com mand. Three additional Truth Tables appear following
the Op er a tion section; these tables provide current state/
next state information.

COMMAND INHIBIT

The COMMAND INHIBIT function pre vents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively
de se lect ed. Op er a tions already in progress are not
affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This pre vents unwanted commands from being registered
dur ing idle or wait states. Op er a tions already in progress
are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-11 (A12
should be driven low). See Mode Reg is ter heading in the
Register Defi ni tion sec tion. The LOAD MODE REGISTER

NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 defi ne the op-code written to the Mode Register and A12 should be driven

low.

3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-9, A11 provide column address; A10 HIGH enables the auto precharge feature

(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks

precharged and BA0, BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is

LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't

Care" except for CKE.

8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs

(two-clock delay).

ADVANCED

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two clocks earlier. If a given DQM signal was registered
HIGH, the cor re spond ing I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.

WRITE

The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-9, A11 se lects the starting column location.
The value on input A10 de ter mines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for sub se quent accesses. Input
data appearing on the I/Os is written to the memory array
subject to the DQM input logic level ap pear ing co in ci dent
with the data. If a given DQM signal is registered LOW,
the cor re spond ing data will be written to memory; if the
DQM signal is registered HIGH, the cor re spond ing data
inputs will be ignored, and a WRITE will not be executed
to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (tRP) after the PRECHARGE command
is is sued. Input A10 determines wheth er one or all banks
are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank.
Oth er wise BA0, BA1 are treated as "Don't Care." Once a
bank has been precharged, it is in the idle state and must
be activated pri or to any READ or WRITE commands being
is sued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the same
in di vid u al-bank PRECHARGE function de scribed above,
with out re quir ing an explicit command. This is ac com plished
by using A10 to enable AUTO PRECHARGE in conjunction
with a spe cifi c READ or WRITE command. A precharge of
the bank/row that is ad dressed with the READ or WRITE
com mand is au to mat i cal ly performed upon com ple tion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not ap ply. AUTO
PRECHARGE is non per sis tent in that it is either enabled or
disabled for each in di vid u al READ or WRITE com mand.

AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must not
is sue another command to the same bank until the precharge

time (t

) is completed. This is determined as if an explicit

PRECHARGE com mand was issued at the earliest possible
time.

BURST TERMINATE

The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
reg is tered READ or WRITE command prior to the BURST
TER MI NATE command will be truncated.

AUTO REFRESH

AUTO REFRESH is used during normal op er a tion of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) RE FRESH in con ven tion al DRAMs. This com mand
is nonpersistent, so it must be issued each time a refresh
is required.

The addressing is generated by the internal refresh
con trol ler. This makes the address bits "Don't Care" during
an AUTO RE FRESH command. Each 512Mb SDRAM
requires 8,192 AUTO RE FRESH cycles every refresh
period (t

REF

). Pro vid ing a dis trib ut ed AUTO RE FRESH

command will meet the refresh re quire ment and ensure
that each row is re freshed. Al ter na tive ly, 8,192 AUTO
RE FRESH com mands can be is sued in a burst at the
minimum cycle rate (t

), once every refresh period

REF

SELF REFRESH*

The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data with out external clocking. The SELF RE FRESH
command is ini ti at ed like an AUTO REFRESH com mand
except CKE is dis abled (LOW). Once the SELF RE FRESH
command is reg is tered, all the inputs to the SDRAM
become "Don't Care," with the exception of CKE, which
must remain LOW.

Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefi nite period
beyond that.

The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defi ned as a signal cycling within timing con straints

* Self refresh available in commercial and industrial tem per a tures only.

ADVANCED

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ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

Voltage on V

, V

CCQ

Supply relative to Vss

-1 to 4.6

Voltage on NC or I/O pins relative to Vss

-1 to 4.6

Operating Temperature TA (Mil)

-55 to +125

°C

Operating Temperature TA (Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +125

°C

NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and
func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this specifi cation is not
implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.

CAPACITANCE (NOTE 2)

Parameter

Symbol

Max

Unit

Input Capacitance: CLK

CI1

TBD

Addresses, BA0-1 Input Capacitance

TBD

Input Capacitance: All other input-only pins

CI2

TBD

Input/Output Capacitance: I/Os

CIO

TBD

BGA THERMAL RESISTANCE

Description

Symbol

Max

Unit

Junction to Ambient (No Airfl ow)

Theta JA

TBD

C/W

Junction to Ball

Theta JB

TBD

C/W

Junction to Case (Top)

Theta JC

TBD

C/W

NOTE:
Refer to Application Note "PBGA Thermal Resistance Correlation" at www.wedc.com in the application notes section for modeling conditions.

spec i fied for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands is sued (a minimum of two clocks) for t

XSR

because time is required for the com ple tion of any internal
refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH
com mands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.

ADVANCED

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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)

, V

CCQ

= +3.3V ± 0.3V; -55°C T

+125°C

Parameter/Condition

Symbol

Min

Max

Units

Supply Voltage

CCQ

3.6

Input High Voltage: Logic 1; All inputs (21)

2 V

+ 0.3

Input Low Voltage: Logic 0; All inputs (21)

-0.3 0.8 V

Input Leakage Current: Any input 0V V

(All other pins not under test = 0V)

µA

Input Leakage Address Current (All other pins not under test = 0V)

-45

µA

Output Leakage Current: I/Os are disabled; 0V

OUT

CCQ

-5

µA

Output Levels:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4 V

0.4 V

ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)

, V

CCQ

= +3.3V ± 0.3V; -55°C T

+125°C

Parameter/Condition

Symbol

Max

Units

-125

-100

Operating Current: Active Mode;
Burst = 2; Read or Write; t

= t

(min); CAS latency = 3 (3, 18, 19)

CC1

990

900

Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after t

RCD

met; No accesses in progress (3, 12, 19)

CC3

405

Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)

CC4

1,035

990

Self Refresh Current: CKE

0.2V (Commercial and Industrial Temperature: -40°C to + 85°C) (27)

CC7

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 1

W364M72V-XSBX

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

(NOTES 5, 6, 8, 9, 11)

Parameter

Symbol

-100

-125

Unit

Min

Max

Min

Max

Access time from CLK (pos. edge)

CL = 3

CL = 2

Address hold time

Address setup time

CLK high-level width

CLK low-level width

Clock cycle time (22)

CL = 3

CL = 2

CKE hold time

CKH

CKE setup time

CKS

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

Data-in hold time

Data-in setup time

Data-out high-impedance time

CL = 3 (10)

CL = 2 (10)

Data-out low-impedance time

1 1

Data-out hold time (load) (26)

3 3

Data-out hold time (no load)

OHN

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows) Commercial, Industrial

REF

Refresh period (8,192 rows) Military

REF

AUTO REFRESH period

RFC

70 70

PRECHARGE command period

20 ns

ACTIVE bank A to ACTIVE bank B command

RRD

Transition time (7)

0.3 1.2

0.3

1.2

WRITE recovery time

(23)

1 CLK + 7ns

(24)

15 15

Exit SELF REFRESH to ACTIVE command

XSR

80 80

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 1

W364M72V-XSBX

AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)

Parameter/Condition

Symbol

-100

-125

Units

READ/WRITE command to READ/WRITE command (17)

CCD

CKE to clock disable or power-down entry mode (14)

CKED

1 1

CKE to clock enable or power-down exit setup mode (14)

PED

DQM to input data delay (17)

DQD

0 0

DQM to data mask during WRITEs

DQM

0 0

DQM to data high-impedance during READs

DQZ

2 2

WRITE command to input data delay (17)

DWD

0 0

Data-in to ACTIVE command (15)

DAL

Data-in to PRECHARGE command (16)

DPL

2 2

Last data-in to burst STOP command (17)

BDL

Last data-in to new READ/WRITE command (17)

CDL

1 1

Last data-in to PRECHARGE command (16)

RDL

2 2

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

MRD

Data-out to high-impedance from PRECHARGE command (17)

CL = 3

ROH

CL = 2

ROH

NOTES:
1. All voltages referenced to V

2. This parameter is not tested but guaranteed by design. f = 1 MHz, T

= 25°C.

3. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper

operation over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO

REFRESH commands, before proper device operation is ensured. (V

and V

CCQ

must be powered up simultaneously.) The two AUTO REFRESH command wake-
ups should be repeated any time the t

REF

refresh re quire ment is exceeded.

7. AC characteristics assume t

= 1ns.

8. In addition to meeting the transition rate specifi cation, the clock and CKE must

transit between V

and V

(or between V

and V

) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

50pF

10. t

defi nes the time at which the output achieves the open circuit condition; it is not

a reference to V

or V

. The last valid data element will meet t

before going

High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V, with timing referenced to 1.5V

crossover point.

12. Other input signals are allowed to transition no more than once every two clocks

and are otherwise at valid V

or V

levels.

13. I

spec i fi ca tions are tested after the device is properly initialized.

14. Timing actually specifi ed by t

CKS

; clock(s) specifi ed as a reference only at minimum

cycle rate.

15. Timing actually specifi ed by t

plus t

; clock(s) specifi ed as a reference only at

minimum cycle rate.

16. Timing actually specifi ed by t

17. Required clocks are specifi ed by JEDEC functionality and are not de pen dent on

any timing parameter.

18. The I

current will decrease as the CAS latency is reduced. This is due to the fact

that the maximum cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. V

overshoot: V

(MAX) = V

CCQ

+ 2V for a pulse width 3ns, and the pulse width

cannot be greater than one third of the cycle rate. V

undershoot: V

(MIN) = -2V

for a pulse width

3ns.

22. The clock frequency must remain constant (stable clock is defi ned as a signal

cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t

, and PRECHARGE com mands).

CKE may be used to reduce the data rate.

23. Auto precharge mode only. The precharge timing budget (t

) begins 7.5ns/7ns

after the fi rst clock delay, after the last WRITE is executed.

24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.

ADVANCED

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