July 2005
Rev. 2
W3DG6463V-D2
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
512MB 2x32Mx64 SDRAM UNBUFFERED
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available in WP (Write Protect) option as:
W3DG6363V-D2
3.3V 0.3V Power Supply
Dual
Rank
168 pin DIMM JEDEC
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The W3DG6463V is a 2x32Mx64 synchronous DRAM
module which consists of sixteen 32Mx8 SDRAM
components in TSOP II package and one 2K EEPROM
in an 8 pin TSSOP package for Serial Presence Detect
which are mounted on a 168 pin DIMM multilayer FR4
Substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
V
SS
29
DQM1
57
DQ18
85
V
SS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
CS1#
142
DQ51
3
DQ1
31
DNU
59
V
CC
87
DQ33
115
RAS#
143
V
CC
4
DQ2
32
V
SS
60
DQ20
88
DQ34
116
V
SS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
V
CC
34
A2
62
*V
REF
90
V
CC
118
A3
146
*V
REF
7
DQ4
35
A4
63
CKE1
91
DQ36
119
A5
147
DNU
8
DQ5
36
A6
64
V
SS
92
DQ37
120
A7
148
V
SS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
V
SS
40
V
CC
68
V
SS
96
V
SS
124
V
CC
152
V
SS
13
DQ9
41
V
CC
69
DQ24
97
DQ41
125
CK1
153
DQ56
14
DQ10
42
CK0
70
DQ25
98
DQ42
126
*A12
154
DQ57
15
DQ11
43
V
SS
71
DQ26
99
DQ43
127
V
SS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
V
CC
101
DQ45
129
CS3#
157
V
CC
18
V
CC
46
DQM2
74
DQ28
102
V
CC
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
*CB0
49
V
CC
77
DQ31
105
*CB4
133
V
CC
161
DQ63
22
*CB1
50
NC
78
V
SS
106
*CB5
134
NC
162
V
SS
23
V
SS
51
NC
79
CK2
107
V
SS
135
NC
163
CK3
24
NC
52
*CB2
80
NC
108
NC
136
*CB6
164
NC
25
NC
53
*CB3
81
WP***
109
NC
137
*CB7
165
**SA0
26
V
CC
54
V
SS
82
**SDA
110
V
CC
138
V
SS
166
**SA1
27
WE#
55
DQ16
83
**SCL
111
CAS#
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
V
DD
112
DQM4
140
DQ49
168
V
CC
PIN NAMES
A0 A11
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CK0-CK3
Clock input
CKE0,CKE1
Clock Enable input
CS0#-CS3#
Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7#
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
SDA
Serial data I/O
SCL
Serial clock
DNU
Do not use
NC
No Connect
WP
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which does not
support SPD.
*** WP available on the WED3DG6363V-D2 only.
July 2005
Rev. 2
W3DG6463V-D2
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FUNCTIONAL BLOCK DIAGRAM
CS#
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM5
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM3
CS#
CS#
cs#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
CS#
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM1
CSO#
CS1#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS2#
CS3#
DQM2
DQM7
DQM6
RAS#
CAS#
WE#
10K
10
10
SCL
SDA
WP
A0
SA0 SA1 SA2
A1
A2
1.5pF
CKE1
CK0/1/2/3
SDRAMs
SDRAMs
SDRAMs
SDRAMs
SDRAM
Every DQpin of SDRAM
To all SDRAMs
Two 0.1uF Capacitors
per each SDRAM
CKE0
DQn
A0 ~ A12, BA0 & 1
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
V
CC
V
SS
V
CC
July 2005
Rev. 2
W3DG6463V-D2
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
16
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C T
A
70C
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 23C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN
1
100
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN
2
100
pF
Input Capacitance (CKE0)
C
IN
3
60
pF
Input Capacitance (CK0-CK3)
C
IN
4
45
pF
Input Capacitance (CS0#,CS3#)
C
IN
5
35
pF
Input Capacitance (DQM0-DQM7)
C
IN
6
20
pF
Input Capacitance (BA0-BA1)
C
IN
7
100
pF
Data input/output capacitance (DQ0-DQ63)
C
OUT
15
pF
July 2005
Rev. 2
W3DG6463V-D2
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, 0C T
A
70C
Parameters
Symbol
Conditions
Versions
Units
Note
133
100
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
1200
1040
mA
1
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE V
IL
(max), t
CC
= 10ns
35
mA
I
CC2PS
CKE & CK V
IL
(max), t
CC
=
35
mA
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
CKE V
IH
(min), CS V
IH
(min), t
CC
=10ns
Input signals are charged one time during 20
320
mA
I
CC2NS
CKE V
IH
(min), CK V
IL
(max), t
CC
=
Input signals are stable
160
mA
Active standby current in power-down
mode
I
CC3P
CKE V
IL
(max), t
CC
= 10ns
100
mA
I
CC3PS
CKE & CK V
IL
(max), t
CC
=
100
Active standby in current non power-
down mode
I
CC3N
CKE V
IH
(min), CS V
IH
(min), t
CC
= 10ns
Input signals are charged one time during 20ns
480
mA
I
CC3NS
CKE V
IH
(min), CK V
IL
(max), t
CC
=
input signals are stable
400
mA
Operating current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CK
1280
1120
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
2000
1760
mA
2
Self refresh current
I
CC6
CKE 0.2V
50
mA
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
July 2005
Rev. 2
W3DG6463V-D2
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
V
CC
, V
CCQ
= +3.3V 0.3V
AC CHARACTERISTICS
SYMBOL
7
7.5
10
UNITS
NOTE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
Access timefrom CLK (pos.edge)
CL = 3
t
AC(3)
5.4
5.4
6
ns
27
CL = 2
t
AC(2)
5.4
6
6
ns
Address hold time
t
AH
0.8
0.8
1
ns
Address setup time
t
AS
1.5
1.5
2
ns
CLK high-level width
t
CH
2.5
2.5
3
ns
CLK low-level width
t
CL
2.5
2.5
3
ns
Clock cycle time
CL = 3
t
CK(3)
7
7.5
8
ns
23
CL = 2
t
CK(2)
7.5
10
10
ns
23
CKE hold time
t
CKH
0.8
0.8
1
ns
CKE setup time
t
CKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
1.5
1.5
2
ns
Data-in hold time
t
DH
0.8
0.8
1
ns
Data-in setup time
t
DS
1.5
1.5
2
ns
Data-out high-impedance time
CL = 3
t
HZ(3)
5.4
5.4
6
ns
10
CL = 2
t
HZ(2)
5.4
6
6
ns
10
Data-out low-impedance time
t
LZ
1
1
1
ns
Data-out hold time (load)
t
OH
2.7
2.7
2.7
ns
Data-out hold time (no load)
t
OHN
1.8
1.8
1.8
ns
28
ACTIVE to PRECHARGE command
t
RAS
37
120,000
44
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
t
RC
60
66
66
ns
ACTIVE to READ or WRITE delay
t
RCD
15
20
20
ns
Refresh period
t
REF
64
64
64
ms
AUTOREFRESH period
t
RFC
66
66
66
ns
PRECHARGE command period
t
RP
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
14
15
15
ns
Transition time
t
T
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
WRITE recovery time
t
WR
1 CLK
+
7ns
1 CLK
+
7.5ns
1 CLK
+
7.5ns
24
14
15
15
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
67
75
80
ns
20
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