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Электронный компонент: W3DG72256V75AD2I-MG

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WV3DG72256V-AD2
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY
2GB 2x128Mx72 SDRAM, REGISTERED
FEATURES
Burst
Mode
Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V 0.3V Power Supply
Dual
Rank
168 Pin DIMM JEDEC
PCB - AD2: 28.58mm (1.125") TYP
DESCRIPTION
The WV3DG72256V is a 2x128Mx72 synchronous DRAM
module which consists of eighteen 256Mx4 stack SDRAM
com po nents (stacked from 128Mx4) in TSOP II package,
two 18 bit Drive ICs for input control signal and one 2Kb
EEPROM in an 8 pin TSSOP package for Serial Presence
Detect which are mounted on a 168 pin DIMM mul ti lay er
FR4 Substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
PIN NAMES
A0 A12
Address Input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CB0-7
Check Bit (Data-In/Data-Out)
CLK0
Clock Input
CKE0
Clock Enable Input
CS0# - CS3#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
V
REF
Power Supply for Reference
REGE
Register Enable
SDA
Serial Data I/O
SCL
Serial Clock
SA0-2
Address in EEPROM
NC
No Connect
* Pins not used in this module.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
PIN
BACK
PIN
BACK
1
V
SS
29
DQM1
57
DQ18
85
V
SS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
CS1#
142
DQ51
3
DQ1
31
NC
59
V
CC
87
DQ33
115
RAS#
143
V
CC
4
DQ2
32
V
SS
60
DQ20
88
DQ34
116
V
SS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
V
CC
34
A2
62
*VREF
90
V
CC
118
A3
146
*V
REF
7
DQ4
35
A4
63
*CKE1
91
DQ36
119
A5
147
REGE
8
DQ5
36
A6
64
V
SS
92
DQ37
120
A7
148
V
SS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
V
SS
40
V
CC
68
V
SS
96
V
SS
124
V
CC
152
V
SS
13
DQ9
41
V
CC
69
DQ24
97
DQ41
125
NC
153
DQ56
14
DQ10
42
CLK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
V
SS
71
DQ26
99
DQ43
127
V
SS
155
DQ58
16
DQ12
44
NC
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
V
CC
101
DQ45
129
CS3#
157
V
CC
18
V
CC
46
DQM2
74
DQ28
102
V
CC
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
NC
76
DQ30
104
DQ47
132
NC
160
DQ62
21
CB0
49
V
CC
77
DQ31
105
CB4
133
V
CC
161
DQ63
22
CB1
50
NC
78
V
SS
106
CB5
134
NC
162
V
SS
23
V
SS
51
NC
79
NC
107
V
SS
135
NC
163
NC
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
WP
109
NC
137
CB7
165
SA0
26
V
CC
54
V
SS
82
SDA
110
V
CC
138
V
SS
166
SA1
27
WE#
55
DQ16
83
SCL
111
CAS#
139
DQ48
167
SA2
28
DQM0
56
DQ17
84
V
CC
112
DQM4
140
DQ49
168
V
CC
WV3DG72256V-AD2
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY*
FUNCTIONAL BLOCK DIAGRAM
BCS1#, B
2
CKE0
BCS0#, B
0
CKE0
B
0
A0~B
0
A12
BDQM0
BCS2, B
1
CKE0
A
3
~A1
0,
BA0
B
0
A
3
~B
0
A
10
, B
0
BA0
B
1
A
3
~B
1
A
10
, B
1
BA0
B
0
A
11
, B
0
A
12
, B
0
BA1
B
0
CKE0, B
1
CKE0
B
2
CKE0,B
3
CKE0
B
1
A
11
, B
1
A
12
, B
1
BA1
BCS2, BCS3
B
0
A
0
, B
0
A
1,
B
0
BA
2
B
1
A
0
, B
1
A
1
,B
1
BA
2
B
0
RAS#, BCAS#, B
0
WE#
B
1
RAS#, BCAS#, B
1
WE#
BCS0, BCS1
BCS3#, B
3
CKE0
PCLK5
DQ0~3
PCLK1
PCLK2
PCLK3
PCLK4
DQ0~7
DQ0~11
DQ0~15
CB0~3
10
DQ32~35
DQ36~39
DQ40~43
DQ44~47
DQ4~7
BDQM4
BDQM5
10
10
10
10
10
10
10
10
PCLK6
DQ16~19
10
PCLK7
DQ20~23
10
PCLK8
PCLK9
REGE
CKE0
CS2#, CS3#
CS0#, CS1#
DQM0, 1, 4, 5
DQM0, 1, 4, 5
RAS#, CAS#, WE#
A
11
, A
12
, BA1
A
0,
A
1
, A
2
DQM2, 3, 6, 7
DQM2, 3, 6, 7
DQ24~27
10
DQ28~31
10k
V
CC
DQ60~63
10
10
12pF
CLK1,2,3
10
12pF
CLK0,2,3
V
SS
V
CC
DQ56~59
10
DQ52~55
10
DQ48~51
10
10
PCLK0
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
B
0
RAS#, B
0
CAS#, B
0
WE#, B
0
BA0, B
0
BA1
B
1
A0~B
1
A12
B
1
RAS#, B
1
CAS#, B
1
WE#, B
1
BA0, B
1
BA1
G
AGND
AV
CC
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
*1
CLK
Cb
Note
1. The actual values of Cb will depend upon the PLL chosen.
FBIN
FBOUT
CDCF2510
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS0, CKE
CTL
Add
DQM
DQ0~3
CLK#
CS1, CKE
CTL
Add
DQM
DQ0~3
BDQM6
BDQM2
BDQM3
LE
OE#
LE
OE#
LE
OE#
74ALVCF162835
74ALVCF162835
74ALVCF162835
SCL
47K
SDA
SA0
SA1
SA2
Serial PD
WP
A0
A1
A2
WV3DG72256V-AD2
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
36
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C
T
A
70
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers
with Tri-State outputs.
CAPACITANCE
T
A
= 25 C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12, BA0-BA1)
C
IN1
15
pF
Input Capacitance (RAS#, CAS#, WE#)
C
IN2
15
pF
Input Capacitance (CKE0)
C
IN3
15
pF
Input Capacitance (CLK0)
C
IN4
20
pF
Input Capacitance (CS0# - CS3#)
C
IN5
15
pF
Input Capacitance (DQM0-DQM7)
C
IN6
15
pF
Data input/output capacitance (DQ0-DQ63), (CB0-BC7)
C
OUT
22
pF
PRELIMINARY*
WV3DG72256V-AD2
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY*
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, 0C
T
A
70C
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
Parameters
Symbol
Conditions
Versions
Units
Note
133/100
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
2,520
mA
1
Precharge Standby Current
in Power Down Mode
I
CC2P
C
KE
V
IL
(max), t
CC
= 10ns
530
mA
I
CC2PS
C
KE
& CLK V
IL
(max), t
CC
=
130
mA
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
C
KE
V
IH
(min), CS V
IH
(min), t
CC
=10ns
Input signals are charged one time during 20
1,170
mA
I
CC2NS
C
KE
V
IH
(min), CLK V
IL
(max), t
CC
=
Input signals are stable
410
mA
Active standby current in
power-down mode
I
CC3P
C
KE
V
IL
(max), t
CC
= 10ns
670
mA
I
CC3PS
C
KE
& CLK V
IL
(max), t
CC
=
270
mA
Active standby in current non power-
down mode
I
CC3N
C
KE
V
IH
(min), CS V
IH
(min), t
CC
= 10ns
Input signals are charged one time during 20ns
1,530
mA
I
CC3NS
C
KE
V
IH
(min), CLK V
IL
(max), t
CC
=
input signals are stable
950
mA
Operating current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
2,610
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
4,590
mA
2
Self refresh current
I
CC6
C
KE
0.2V
420
mA
WV3DG72256V-AD2
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
AC OPERATING TEST CONDITIONS
V
CC
= 3.3V, 0C
T
A
70C
Parameter
Value
Units
AC Input level (V
IN
/V
IL
)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
AC OPERATING TEST CONDITIONS
Parameter
Symbol
Value
Units
Notes
133/100
Row active to row active delay
t
RRD(MIN)
15
ns
1
RAS# to CAS# delay
t
RCD(MIN)
20
ns
1
Row Precharge time
t
RP(MIN)
20
ns
1
Row active time
t
RAS(MIN)
45
ns
1
t
RAS(MAX)
100
s
Row cycle time
t
RC(MIN)
65
ns
1
Last data in to row precharge
t
RDL(MIN)
2
CLK
2
Last data in to Active delay
t
DAL(MIN)
2 CLK + t
RP
--
Last data in to new col. address delay
t
CDL(MIN)
1
CLK
1
Last data in to burst stop
t
BDL(MIN)
1
CLK
2
Col. address to col. address delay
t
CCD(MIN)
1
CLK
2
Number of valid output data
CAS Latency = 3
2
CLK
3
Cas Latency = 2
1
ea
4
Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
3.3V
1220
870
Output
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=2.4V, I
OL
=-2mA
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
50pF
V
TT
=1.4V
50
Output
50pF
Z0 = 50
PRELIMINARY*
WV3DG72256V-AD2
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
OPERATING AC PARAMETER
Parameter
Symbol
133/100
Units
Notes
Min
Max
CLK cycle time
CAS latency = 3
t
CC
7.5
1,000
ns
1
CAS latency = 2
CLK to valid output delay
CAS latency = 3
t
SAC
5.4
ns
1, 2
CAS latency = 2
Output data hold time
CAS latency = 3
t
OH
3
ns
2
CAS latency = 2
CLK high pulse width
t
CH
2.5
ns
3
CLK low pulse width
t
CL
2.5
ns
3
Input setup time
t
SS
1.5
ns
3
Input hold time
t
SH
0.8
ns
3
CLK to output in Low-z
t
SLZ
1
ns
2
CLK to output in Hi-z
CAS latency = 3
t
HZ
5.4
ns
CAS latency = 2
Notes: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time
compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter.
PRELIMINARY*
WV3DG72256V-AD2
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY*
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
PACKAGE DIMENSIONS FOR AD2
133.350
5.250
127.350
5.014
8.86 Max
(0.270 Max)
1.2700.10
0.0500.0039
2.000
0.079
0.157 0.004
(4.000 0.100)
6.350
0.250
36.830
1.450
54.64
2.150
3.000
0.118
3.00
0.118
8.890
0.350
17.780
0.700
2.540 Min
0.100 Min
0.165 Min
4.19 Min
118DIA 0.004
3.000DIA 0.100
?
6.350
0.250
11.430
(0.450)
115.57
4.550
1.372
0.054
28.575 TYP
1.125
ORDERING INFORMATION FOR AD2
Part Number
Clock Speed
CAS Latency
Height*
WV3DG72256V10AD2xx
100MHz
CL=2
28.58 (1.25") TYP
WV3DG72256V7AD2xx
133MHz
CL=2
28.58 (1.25") TYP
WV3DG72256V75AD2xx
133MHz
CL=3
28.58 (1.25") TYP
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
WV3DG72256V-AD2
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY*
PART NUMBERING GUIDE
WV 3 D G 72 256 V xx AD2 I- x G
WEDC
MEMORY
SDRAM
GOLD
BUS WIDTH
DEPTH
3.3 VOLTS
CLOCK SPEED (MHz)
10 = 100MHz @ CL = 2
7 = 133MHz @ CL = 2
75 = 133MHz @ CL = 3
PACKAGE 168 PIN DIMM
AD2: 28.58mm (1.125")
INDUSTRIAL TEMP
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
WV3DG72256V-AD2
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
PRELIMINARY*
Document Title
2GB- 2x128Mx72 SDRAM, REGISTERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created Data sheet
January 2006
Advanced