W3DG72256V-D2
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
2GB 256Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst
Mode
Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V 0.3V Power Supply
168
Pin
DIMM
JEDEC
PCB - D2: 37.34mm (1.47")
DESCRIPTION
The W3DG72256V is a 256Mx72 synchronous DRAM
module which consists of eighteen 256Mx4 stack SDRAM
com po nents in TSOP II package, two 18 bit Drive ICs for
input control signal and one 2Kb EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 pin DIMM mul ti lay er FR4 Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
PIN NAMES
A0 A12
Address Input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CB0-7
Check Bit (Data-In/Data-Out)
CK0
Clock Input
CKE0
Clock Enable Input
CS0#, CS3#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
*V
REF
Power Supply for Reference
REGE
Register Enable
SDA
Serial Data I/O
SCL
Serial Clock
SA0-2
Address in EEPROM
DNU
Do Not Use
NC
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
PIN
BACK
PIN
BACK
1
V
SS
29
DQM1
57
DQ18
85
V
SS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
CS1#
142
DQ51
3
DQ1
31
DNU
59
V
CC
87
DQ33
115
RAS#
143
V
CC
4
DQ2
32
V
SS
60
DQ20
88
DQ34
116
V
SS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
V
CC
34
A2
62
*VREF
90
V
CC
118
A3
146
*V
REF
7
DQ4
35
A4
63
*CKE1
91
DQ36
119
A5
147
REGE
8
DQ5
36
A6
64
V
SS
92
DQ37
120
A7
148
V
SS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
V
SS
40
V
CC
68
V
SS
96
V
SS
124
V
CC
152
V
SS
13
DQ9
41
V
CC
69
DQ24
97
DQ41
125
*CK1
153
DQ56
14
DQ10
42
CK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
V
SS
71
DQ26
99
DQ43
127
V
SS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
V
CC
101
DQ45
129
CS3#
157
V
CC
18
V
CC
46
DQM2
74
DQ28
102
V
CC
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
CB0
49
V
CC
77
DQ31
105
CB4
133
V
CC
161
DQ63
22
CB1
50
NC
78
V
SS
106
CB5
134
NC
162
V
SS
23
V
SS
51
NC
79
*CK2
107
V
SS
135
NC
163
*CK3
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
NC
109
NC
137
CB7
165
**SA0
26
V
CC
54
V
SS
82
**SDA
110
V
CC
138
V
SS
166
**SA1
27
WE#
55
DQ16
83
**SCL
111
CAS#
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
V
CC
112
DQM4
140
DQ49
168
V
CC
W3DG72256V-D2
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
FUNCTIONAL BLOCK DIAGRAM
REGE
PCK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
CS0#
DQMB0
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQMB4
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQMB1
DQMB5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQMB2
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQMB6
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQMB3
DQMB7
V
CC
V
SS
SDRAMs
SDRAMs
CB0
CB1
CB2
CB3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
* Wire per Clock Loading Table/Wiring Diagrams
NOTE: DQ wiring may differ than described in
this drawing, however DQ/DQMB/CKE/S
relationships must be maintained as shown.
RAS#: SDRAMS
CAS#: SDRAMS
CKE0: SDRAMS
WE#: SDRAMS
CS0#-CS3#
DQMB0 to DQMB7
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
WE#
CKE1
RS0#-RS3#
RDQMB0-RDQMB7
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
R
E
G
I
S
T
E
R
CKE1: SDRAMS
CS1#
CS2#
CS3#
#
RBA0-RBA1
RA0-RA12
BA0-BA1: SDRAMS
A0-A12: SDRAMS
A0
SERIAL PD
A1
A2
SA0
SA1
SA2
SCL
SDA
CK0
CK1-CK3
12pF
PLL
REGISTER
SDRAM
12pF
NOTE: All resistor values are 10 ohms.
W3DG72256V-D2
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
36
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C
T
A
70
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers
with Tri-State outputs.
CAPACITANCE
T
A
= 25 C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
9
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
9
pF
Input Capacitance (CKE0)
C
IN3
9
pF
Input Capacitance (CLK0)
C
IN4
17
pF
Input Capacitance (CS0#,CS2#)
C
IN5
9
pF
Input Capacitance (DQM0-DQM7)
C
IN6
7
pF
Input Capacitance (BA0-BA1)
C
IN7
9
pF
Data input/output capacitance (DQ0-DQ63)
C
OUT
16
pF
Data input/output capacitance (CB0-CB7)
C
OUT1
16
pF
W3DG72256V-D2
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, 0C
T
A
70C
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive ICs.
Parameters
Symbol
Conditions
Versions
Units
Note
133/100
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
7525
mA
1
Precharge Standby Current
in Power Down Mode
I
CC2P
C
KE
V
IL
(max), t
CC
= 10ns
541
mA
3
I
CC2PS
C
KE
& CLK V
IL
(max), t
CC
=
450
mA
3
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
C
KE
V
IH
(min), CS V
IH
(min), t
CC
=10ns
Input signals are charged one time during 20
1405
mA
3
I
CC2NS
C
KE
V
IH
(min), CLK V
IL
(max), t
CC
=
Input signals are stable
468
mA
3
Active standby current in
power-down mode
I
CC3P
C
KE
V
IL
(max), t
CC
= 10ns
468
mA
3
I
CC3PS
C
KE
& CLK V
IL
(max), t
CC
=
375
mA
3
Active standby in current non power-
down mode
I
CC3N
C
KE
V
IH
(min), CS V
IH
(min), t
CC
= 10ns
Input signals are charged one time during 20ns
2125
mA
3
I
CC3NS
C
KE
V
IH
(min), CLK V
IL
(max), t
CC
=
input signals are stable
1487
mA
3
Operating current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
7525
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
12205
mA
2
Self refresh current
I
CC6
C
KE
0.2V
577
mA
3
W3DG72256V-D2
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
PACKAGE DIMENSIONS FOR D2
3.99
(0.157)
MIN.
6.60
(0.260) MAX.
1.27 0.10
(0.050 .004)
11.43
(0.450)
54.61 (2.150)
133.35 (5.250)
37.34
(1.470)
17.78
(0.700)
6.35 (0.250)
115.57 (4.550)
(0.000)
36.83 (1.450)
6.35 (0.250)
57.79 (2.275)
3.18 (0.125) (2X)
3.99
(0.157
0.004)
(2X)
P1
(0.000)
3.10
(0.122)
8.89
(0.350)
15.60
(0.614)
ORDERING INFORMATION FOR D2
Part Number
Speed
CAS Latency
Height*
W3DG72256V10D2
100MHz
CL=2
37.34 (1.47")
W3DG72256V7D2
133MHz
CL=2
37.34 (1.47")
W3DG72256V75D2
133MHz
CL=3
37.34 (1.47")
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
W3DG72256V-D2
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 3
Document Title
2GB- 256Mx72 SDRAM, REGISTER and SPD, w/PLL
Revision History
Rev #
History
Release Date
Status
Rev A
Created Datasheet
11-6-01
Advanced
Rev B
B.1 Corrected block diagram
B.2 Change module height to 1.10"
1-22-02
Advanced
Rev C
C.1 Pg. 5 corrected spec.
Pg. 6 corrected module width dimension
2.2 Changed from advanced to preliminary
3-25-02
Advanced
Rev 0
Changed from Advanced to Final
9-19-02
Final
Rev 1
Changed mechanical package dimensions
1-22-04
Final
Rev 2
2.1 Updated CAP and I
DD
Specs
2.2 Removed "ED" from part number
6-1-04
Final
Rev 3
3.1 Correction to module
Height changed from 1.10" to 1.47"
8-05
Final
PDF 
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