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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY*
256MB - 32Mx72 SDRAM UNBUFFERED
DESCRIPTION
The W3DG7237V is a 32Mx72 synchronous DRAM
module which consists of nine 32Mx8 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 pin DIMM multilayer FR4 Substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
FEATURES
PC100
and
PC133
Burst
Mode
Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V 0.3V Power Supply
JEDEC standard 168 Pin DIMM
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
A0 A12
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CB0-7
Check bit (Data-in/data-out)
CLK0,CLK2
Clock input
CKE0
Clock Enable input
CS0#,CS2# Chip
select
Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
*V
REF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
SA0-2
Address in EEPROM
DNU
Do not use
NC
No Connect
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
V
SS
29
DQM1
57
DQ18
85
V
SS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
*CS1#
142
DQ51
3
DQ1
31
DNU
59
V
CC
87
DQ33
115
RAS#
143
V
CC
4
DQ2
32
V
SS
60
DQ20
88
DQ34
116
V
SS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
V
CC
34
A2
62
*V
REF
90
V
CC
118
A3
146
*V
REF
7
DQ4
35
A4
63
*CKE1
91
DQ36
119
A5
147
NC
8
DQ5
36
A6
64
V
SS
92
DQ37
120
A7
148
V
SS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
V
SS
40
V
CC
68
V
SS
96
V
SS
124
V
CC
152
V
SS
13
DQ9
41
V
CC
69
DQ24
97
DQ41
125
*CLK1
153
DQ56
14
DQ10
42
CK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
V
SS
71
DQ26
99
DQ43
127
V
SS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
V
CC
101
DQ45
129
*CS3#
157
V
CC
18
V
CC
46
DQM2
74
DQ28
102
V
CC
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
CB0
49
V
CC
77
DQ31
105
CB4
133
V
CC
161
DQ63
22
CB1
50
NC
78
V
SS
106
CB5
134
NC
162
V
SS
23
Vss
51
NC
79
CLK2
107
V
SS
135
NC
163
*CLK3
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
NC
109
NC
137
CB7
165
**SA0
26
V
CC
54
V
SS
82
**SDA
110
V
CC
138
V
SS
166
**SA1
27
WE#
55
DQ16
83
**SCL
111
CAS#
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
V
CC
112
DQM4
140
DQ49
168
V
CC
* These pins are not used in this module.
** These pins should be NC in the system which does not
support
SPD.
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
DQM1
DQM5
DQM3
DQM2
CS2#
V
CC
Vss
One 0.1uF and one 0.22 uF Cap.
per each SDRAM
To all SDRAMs
A0 ~ A12, BA0 & 1
CKE0
RAS#
CAS#
WE#
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
10
DQn
Every DQpin of SDRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
CS#
DQM0
CS0#
DQM4
DQM6
DQM7
CLK1/3
10
10pF
Serial PD
SDA
SCL
A1
A2
A0
SA1 SA2
SA0
WP
47K
* Clock Wiring
Clock Input
SDRAMS
CLK0
4 SDRAMS
CLK2
5 SDRAMS
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
9
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C
T
A
70
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25 C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
40
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
40
pF
Input Capacitance (CKE0)
C
IN3
40
pF
Input Capacitance (CLK0)
C
IN4
20
pF
Input Capacitance (CS0#,CS2#)
C
IN5
24
pF
Input Capacitance (DQM0-DQM7)
C
IN6
7
pF
Input Capacitance (BA0-BA1)
C
IN7
40
pF
Data input/output capacitance (DQ0-DQ63)
C
OUT
9
pF
Data input/output capacitance (CB0-CB7)
C
OUT1
9
pF
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, 0C
T
A
70C
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
Parameters
Symbol
Conditions
Versions
Units
Note
133/100
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
720
mA
1
Standby Current
in Power Down Mode
I
CC2
C
KE
V
IL
(max), t
CC
= 10ns
18
mA
Active standby in current non power-down
mode
I
CC3
C
KE
V
IH
(min), CS V
IH
(min), t
CC
= 10ns
Input signals are charged one time during 20ns
225
mA
Operating current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
900
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
1620
mA
2
Self refresh current
I
CC6
C
KE
0.2V
27
mA
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
PACKAGE DIMENSIONS
ORDERING INFORMATION
Part Number
Speed
CAS Latency
Height*
W3DG7237V10D2
100MHz
CL=2
30.48 (1.20")
W3DG7237V7D2
133MHz
CL=2
30.48 (1.20")
W3DG7237V75D2
133MHz
CL=3
30.48 (1.20")
17.78
(0.700)
30.48
(1.20)
MAX
24.49
(0.964)
1.98
(0.078)
(2X)
6.35
(0.250)
36.83
(1.450)
42.19
(1.661)
3.18
(0.125)
54.61
(2.150)
1.27
(0.050) TYP.
1.27 0.10
(0.050 0039)
8.88
(0.350)
11.43
(0.450)
3.99
(0.157)
(2X)
3.05
(0.120)
MAX
3.99
(0.157)
133.48
(5.255) MAX.
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3DG7237V-D2
June 2004
Rev. 0
PRELIMINARY
Document Title
256MB- 32Mx72 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev A
Created
11-6-01
Advanced
Rev B
Add "Part Number" to order info table
11-16-02
Advanced
Rev 0
0.1 Updated Cap & I
DD
Specs
0.2 Changed status from Advanced to Preliminary
6-04
Preliminary
PDF 
ZIP