W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY*

512MB 64Mx72 SDRAM, REGISTER and SPD, w/PLL

DESCRIPTION

The W3DG7266V is a 64Mx72 synchronous DRAM
module which consists of nine 64Mx8 SDRAM components
in TSOP II package, two 18 bit Drive ICs for input control
signal and one 2Kb EEPROM in an 8 pin TSSOP package
for Serial Presence Detect which are mounted on a 168
pin DIMM mul ti lay er FR4 Substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

NOTE: Consult factory for availability of:

Lead-Free

Products

· Vendor source control options
· Industrial temperature option

FEATURES

Burst

Mode

Operation

Auto and Self Refresh capability

LVTTL compatible inputs and outputs

Serial Presence Detect with EEPROM

Fully synchronous: All signals are registered on the positive
edge of the system clock

Programmable Burst Lengths: 1, 2, 4, 8 or Full Page

3.3V

± 0.3V Power Supply

168 Pin DIMM JEDEC

· PCB: 30.49mm (1.20") MAX

PIN NAMES

A0 A12

Address Input (Multiplexed)

BA0-1

Select Bank

DQ0-63

Data Input/Output

CB0-7

Check Bit (Data-In/Data-Out)

CK0

Clock Input

CKE0

Clock Enable Input

CS0#, CS2#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQM0-7

DQM

Power Supply (3.3V)

Ground

REF

Power Supply for Reference

REGE

SDA

Serial Data I/O

SCL

Serial Clock

SA0-2

Address in EEPROM

DNU

Do Not Use

No Connect

* These pins are not used in this module.
** These pins should be NC in the system which does

not support SPD.

PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)

FRONT

BACK

FRONT

BACK

DQM1

DQ18

113

DQM5

141

DQ50

DQ0

CS0#

DQ19

DQ32

114

*CS1#

142

DQ51

DQ1

DNU

DQ33

115

RAS#

143

DQ2

DQ20

DQ34

116

144

DQ52

DQ3

DQ35

117

145

REF

118

146

REF

DQ4

*CKE1

DQ36

119

147

REGE

DQ5

DQ37

120

148

DQ6

DQ21

DQ38

121

149

DQ53

DQ7

A10/AP

DQ22

DQ39

122

BA0

150

DQ54

DQ8

BA1

DQ23

DQ40

123

A11

151

DQ55

124

152

DQ9

DQ24

DQ41

125

*CK1

153

DQ56

DQ10

CK0

DQ25

DQ42

126

A12

154

DQ57

DQ11

DQ26

DQ43

127

155

DQ58

DQ12

DNU

DQ27

100

DQ44

128

CKE0

156

DQ59

DQ13

CS2#

101

DQ45

129

*CS3#

157

DQM2

DQ28

102

130

DQM6

158

DQ60

DQ14

DQM3

DQ29

103

DQ46

131

DQM7

159

DQ61

DQ15

DNU

DQ30

104

DQ47

132

*A13

160

DQ62

CB0

DQ31

105

CB4

133

161

DQ63

CB1

106

CB5

134

162

*CK2

107

135

163

*CK3

CB2

108

136

CB6

164

CB3

109

137

CB7

165

**SA0

**SDA

110

138

166

**SA1

WE#

DQ16

**SCL

111

CAS#

139

DQ48

167

*SA2

DQM0

DQ17

112

DQM4

140

DQ49

168

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

REGE

PCK

DQMB3

DQMB2

DQ0

DQ1

DQ2

DQ3

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQMB0

DQ4

DQ5

DQ6

DQ7

I/O 4

I/O 5

I/O 6

I/O 7

DQ8

DQ9

DQ10

DQ11

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ12

DQ13

DQ14

DQ15

I/O 4

I/O 5

I/O 6

I/O 7

DQ16

DQ17

DQ18

DQ19

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ20

DQ21

DQ22

DQ23

I/O 4

I/O 5

I/O 6

I/O 7

DQ24

DQ25

DQ26

DQ27

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ28

DQ29

DQ30

DQ31

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQMB4

DQ44

DQ45

DQ46

DQ47

I/O 4

I/O 5

I/O 6

I/O 7

DQ48

DQ49

DQ50

DQ51

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ52

DQ53

DQ54

DQ55

I/O 4

I/O 5

I/O 6

I/O 7

DQ56

DQ57

DQ58

DQ59

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ60

DQ61

DQ62

DQ63

I/O 4

I/O 5

I/O 6

I/O 7

CB0

CB1

CB2

CB3

DQM

I/O 0

I/O 1

I/O 2

I/O 3

CB4

CB5

CB6

CB7

I/O 4

I/O 5

I/O 6

I/O 7

DQMB1

DQ32

DQ33

DQ34

DQ35

DQM

I/O 0

I/O 1

I/O 2

I/O 3

DQ36

DQ37

DQ38

DQ39

I/O 4

I/O 5

I/O 6

I/O 7

DQMB5

DQMB6

DQMB7

CS0#

CS2#

SDRAM

* Wire per Clock Loading Table/Wiring Diagrams

NOTE: DQ wiring may differ than described in
this drawing, however DQ/DQMB/CKE/S
relationships must be maintained as shown.

CS0# - CS2#

DQMB0 - DQMB7

BA0 - BA1

A0 - A12

RAS#
CAS#
CKE0

WE#

RCS0# - RCS2#
RDQMB0 - RDQMB7

RRAS#: SDRAMS
RCAS#: SDRAMS
RCKE0: SDRAMS
RWE#: SDRAMS

R
E
G

S
T
E
R

RBA0 - RBA1: SDRAMS
RA0 - RA12: SDRAMS

SERIAL PD

SA0

SA1

SA2

SCL

CK1-CK3

SDA

12pF

10ohm

PLL

CK0

SDRAM

10 ohm

12pF

NOTE: All resistor values are 10 ohms.

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 ~ 4.6

Storage Temperature

STG

-55 ~ +150

°C

Power Dissipation

Short Circuit Current

Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

Voltage Referenced to: V

= 0V, 0°C T

70°C

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply Voltage

3.0

3.3 3.6

Input High Voltage

2.0

3.0

CCQ

+0.3

Input Low Voltage

-0.3

0.8

Output High Voltage

2.4

= -2mA

Output Low Voltage

0.4

= -2mA

Input Leakage Current

-10

Note: 1. V

(max)= 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min)= -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V V

CCQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

= 25 °C, f = 1MHz, V

= 3.3V, V

REF

= 1.4V ± 200mV

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A11)

IN1

Input Capacitance (RAS#,CAS#,WE#)

IN2

Input Capacitance (CKE0)

IN3

Input Capacitance (CLK0)

IN4

Input Capacitance (CS0#,CS2#)

IN5

Input Capacitance (DQM0-DQM7)

IN6

Input Capacitance (BA0-BA1)

IN7

Data input/output capacitance (DQ0-DQ63)

OUT

Data input/output capacitance (CB0-CB7)

OUT1

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

OPERATING CURRENT CHARACTERISTICS

= 3.3V, 0°C

70°C

Parameters

Symbol

Conditions

Versions

Units

Note

133/100

Operating Current
(One bank active)

CC1

Burst Length = 1
t

(min)

= 0mA

1080

Standby Current
in Power Down Mode

CC2

(max), t

= 10ns

Active standby in current non power-down
mode

CC3

(min), CS V

(min), t

= 10ns

Input signals are charged one time during 20ns

405

Operating current (Burst mode)

CC4

Io = mA
Page burst
4 Banks activated
t

CCD

= 2CLK

1125

Refresh current

CC5

(min)

2295

Self refresh current

CC6

0.2V

Notes: 1. Measured with outputs open.

2. Refresh period is 64ms.

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

, V

CCQ

= +3.3V ±0.3V

AC CHARACTERISTICS

SYMBOL

7.5

UNITS

NOTE

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

Access timefrom CLK (pos.edge)

CL = 3

AC(3)

5.4

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

2.7

Data-out hold time (no load)

OHN

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period

REF

AUTOREFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK

7ns

1 CLK

7.5ns

1 CLK

7.5ns

Exit SELF REFRESH to ACTIVE command

XSR

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

AC FUNCTIONAL CHARACTERISTICS

, V

CCQ

= +3.3V ±0.3V

PARAMETER

SYMBOL

7.5

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQMto data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-into ACTIVE command

DAL

15, 21

Data-into PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Lastdata-into PRECHARGE command

RDL

16, 21

LOADMODEREGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

Notes
1.

All voltages referenced to V

This parameter is sampled. V

, V

CCQ

= +3.3V; T

= 25°C; pin under test biased

at 1.4V; f = 1 MHz.

3. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with mini-mum cycle time and the outputs open.

Enables on-chip refresh and address counters.

The minimum specifi cations are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.

An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (V

and V

CCQ

must be powered up simultaneously. V

and V

SSQ

must be at same potential.)

The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.

AC characteristics assume t

= 1ns.

In addition to meeting the transition rate specifi cation, the clock and CKE must
transit between V

and V

(or between V

and V

) in a mono-tonic manner.

Outputs measured at 1.5V with equivalent load:

50pF

10. t

defi nes the time at which the output achieves the open circuit condition; it is

not a reference to V

or V

. The last valid data element will meet t

before

going High-Z.

11.

AC timing and I

tests have V

= 0V and V

= 3V with timing referenced to 1.5V

crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at V

(MAX) and V

(MIN) and no longer at the 1.5V crossover point.

12.

Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid V

or V

levels.

13. I

specifi cations are tested after the device is properly initialized.

14.

Timing actually specifi ed by t

CKS

; clock(s) specifi ed as a reference only at

minimum cycle rate.

15.

Timing actually specifi ed by t

plus t

; clock(s) specifi ed as a reference only at

minimum cycle rate.

16.

Timing actually specifi ed by t

17.

Required clocks are specifi ed by JEDEC functionality and are not dependent on
any timing parameter.

18. The

current will increase or decrease proportionally according to the amount

of frequency alteration for the test condition.

19.

Address transitions average one transition every two clocks.

20.

CLK must be toggled a minimum of two times during this period.

21.

Based on t

= 10ns for 10, and t

= 7.5ns for 7 and 7.5.

22. V

overshoot: V

(MAX) = V

CCQ

+ 2V for a pulse width 3ns, and the pulse

width cannot be greater than one third of the cycle rate. V

under-shoot: V

(MIN) = -2V for a pulse width 3ns.

23.

The clock frequency must remain constant (stable clock is defi ned as a signal
cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t

, and PRECHARGE commands).

CKE may be used to reduce the data rate.

24.

Auto precharge mode only. The precharge timing budget (t

) begins 7ns for 7;

7.5ns for 7.5 and 7.5ns for 10 after the fi rst clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.

25. Precharge

mode

only.

26.

JEDEC and PC133, PC100 specify three clocks.

27. t

for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.

28.

Parameter guaranteed by design.

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

17.78

(0.700)

30.48

(1.20)

MAX.

3.99

(0.157)

MIN.

1.27 ± 0.10

(0.050 ± 0.004)

MEASURED AFTER

PLATING

OVER FINGERS.

4.32

(0.170)

MAX.

133.48 (5.255)

MAX.

SEE NOTE 1

54.61

(2.150)

6.35

(0.250)

115.57

(4.550)

42.19

(1.661)

36.83

(1.450)

6.35

(0.250)

3.18

(0.125)

(2X)

15.60

(0.614)

11.43

(0.450)

3.99

(0.157)

(2X)

ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

PACKAGE DIMENSIONS

ORDERING INFORMATION FOR D2

Part Number

Speed

CAS Latency

Height*

W3DG7266V10D2

100MHz

CL=2

30.48 (1.20")

W3DG7266V7D2

133MHz

CL=2

30.48 (1.20")

W3DG7266V75D2

133MHz

CL=3

30.48 (1.20")

NOTES:

· Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is

shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult
factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

W3DG7266V-D2

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

May 2005
Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

PRELIMINARY

Document Title

512MB 64Mx72 SDRAM, REGISTER and SPD, w/PLL

Revision History

Rev #

History

Release Date

Status

Rev A

Create

2-21-02

Advanced

Rev 1

1.1 Updated CAP and I

Specs

1.2 Removed "ED" from part number

1.3 Added new title page

1.4 Moved from Advanced to Preliminary

8-2004

Preliminary

Rev 2

2.1 Added AC specs

3.2 Provided lead-free and RoHS notes

2.3 Added source control notes

2.4 Added industiral temperature note

2-05

Preliminary

Rev 3

3.1 Updated CAP specs

3.2 Updated I

specs

5-05

Preliminary

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W3DG7266V10D2

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W3DG7266V10D2