White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY*

W3DG7268V-AD1

512MB- 64Mx72 SDRAM UNBUFFERED

DESCRIPTION

The W3DG7268V is a 64Mx72 synchronous DRAM module
which consists of nine 64Mx8 SDRAM com po nents in
TSOP II package, and one 2K EEPROM in an 8 pin TSSOP
package for Serial Presence Detect which are mounted on
a 144 Pin SO-DIMM mul ti lay er FR4 Substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

FEATURES

PC100 and PC133 Compatible

Burst

Mode

Operation

Auto and Self Refresh capability

LVTTL compatible inputs and outputs

Serial Presence Detect with EEPROM

Fully synchronous: All signals are registered on the
positive edge of the system clock

Programmable Burst Lengths: 1, 2, 4, 8 or Full Page

3.3V ± 0.3V Power Supply

144

SO-DIMM

· Package height option:

AD1: 27.94 (1.10")

PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)

PIN NAMES

A0 A12

Address input (Multiplexed)

BA0-1

Select Bank

DQ0-63

Data Input/Output

CB0-7

Check bit (Data-in/data-out)

CLK0,CK1

Clock input

CKE0

Clock Enable input

CS0#

Chip select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQMB0-7

DQM

Power Supply (3.3V)

Ground

SDA

Serial data I/O

SCL

Serial clock

DNU

Do not use

No Connect

PIN FRONT PIN

BACK

PIN FRONT PIN

BACK

PIN FRONT PIN

BACK

DQ13

DQ45

DQ22

DQ54

DQ0

DQ32

DQ14

DQ46

DQ23

100

DQ55

DQ1

DQ33

DQ15

DQ47

101

102

DQ2

DQ34

103

104

DQ3

DQ35

CB0

CB4

105

106

BA0

CB1

CB5

107

108

DQ4

DQ36

CLK0

CKE0

109

110

BA1

DQ5

DQ37

111

A10

112

A11

DQ6

DQ38

RAS#

CAS#

113

114

DQ7

DQ39

WE#

115 DQMB2 116 DQMB6

CS0#

A12

117 DQMB3 118 DQMB7

23 DQMB0 24

DQB4

119

120

25 DQMB1 26

DQB5

CLK1

121

DQ24

122

DQ56

123

DQ25

124

DQ57

CB2

CB6

125

DQ26

126

DQ58

CB3

CB7

127

DQ27

128

DQ59

129

130

DQ16

DQ48

131

DQ28

132

DQ60

DQ8

DQ40

DQ17

DQ49

133

DQ29

134

DQ61

DQ9

DQ41

DQ18

DQ50

135

DQ30

136

DQ62

DQ10

DQ42

DQ19

DQ51

137

DQ31

138

DQ63

DQ11

DQ43

VSS

139

140

DQ20

DQ52

141

SDA

142

SCL

DQ12

DQ44

DQ21

DQ53

143

144

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

DQMB0

WE#

DQ0
DQ1

DQ2

DQ3
DQ4
DQ5

DQ6

DQ7

CS0#

DQM

WE#

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

WE#

DQM

CS0#

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

WE#

DQM

CS0#

WE#

DQM

CS0#

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

WE#

DQM

CS0#

DQ62

DQ63

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ47

DQ51

DQ55

DQ54

DQ53

DQ52

DQ49

DQ50

DQ48

DQ43

DQ45

DQ46

DQ44

DQ41

DQ42

DQ40

DQ39

DQ37

DQ38

DQ35
DQ36

DQ33

DQ34

DQ32

WE#

DQM

CS0#

DQM

CS0#

WE#

CS0#

DQM

WE#

DQM

CS0#

DQMB1

DQMB2

DQMB3

DQMB7

DQMB6

DQMB5

DQMB4

I/O 0
I/O 1

I/O 2

I/O 3
I/O 4
I/O 5

I/O 6

I/O 7

I/O 3

I/O 7

I/O 6

I/O 5

I/O 4

I/O 2

I/O 1

I/O 0

I/O 3

I/O 7

I/O 6

I/O 5

I/O 4

I/O 2

I/O 1

I/O 0

I/O 3

I/O 7

I/O 6

I/O 5

I/O 4

I/O 2

I/O 1

I/O 0

I/O 3

I/O 7

I/O 6

I/O 5

I/O 4

I/O 2

I/O 1

I/O 0

I/O 3

I/O 7

I/O 6

I/O 5

I/O 4

I/O 2

I/O 1

I/O 0

I/O 7

I/O 0
I/O 1

I/O 2

I/O 4
I/O 5

I/O 6

I/O 3

I/O 3
I/O 4

I/O 5

I/O 6

I/O 7

I/O 0
I/O 1

I/O 2

I/O 0
I/O 1

I/O 2

I/O 4
I/O 5

I/O 6

I/O 7

I/O 3

CB3

CB6

CB7

CB4
CB5

CB1

CB2

CB0

CAS#

RAS#

CKE0

CKE: SDRAM D0-D8

CAS#: SDRAM D0-D8

RAS#: SDRAM D0-D8

SCL

SDA

SERIAL PD

A0-A12: SDRAM D0-D8

A0-A12

BA0-BA1

BA0-BA1: SDRAM D0-D8

D0-D8

*CLOCK WIRING

CLOCK
INPUT

SDRAMS

*CLK0

*CLK1

5 SDRAMS

4 SDRAMS

*Wire per Clock Loading Table/Wiring Diagrams

Note: DQ wiring may differ than
described in this drawing, however
DQ/DQMB/CKE/S relationships must
be maintained as shown.

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 ~ 4.6

Storage Temperature

STG

-55 ~ +150

°C

Power Dissipation

9 W

Short Circuit Current

Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply Voltage

3.0

3.3 3.6

Input High Voltage

2.0

3.0

CCQ+0.3

Input Low Voltage

-0.3

0.8

Output High Voltage

2.4

= -2mA

Output Low Voltage

0.4

= +2mA

Input Leakage Current

-10

µA

Note:
1. V

(max)= 5.6V AC. The overshoot voltage duration is 3ns.

2. V

(min)= -2.0V AC. The undershoot voltage duration is 3ns.

3. Any input 0V V

CCQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

= 25°C, f = 1MHz, V

= 3.3V, V

REF

= 1.4V ± 200mV

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

Input Capacitance (RAS#,CAS#,WE#)

IN2

Input Capacitance (CKE0)

IN3

Input Capacitance (CK0)

IN4

Input Capacitance (CS0#)

IN5

Input Capacitance (DQM0-DQM7)

IN6

Input Capacitance (BA0-BA1)

IN7

Data Input/Output Capacitance (DQ0-DQ63)

OUT

Data input/output capacitance (CB0-CB7)

OUT1

RECOMMENDED DC OPERATING CONDITIONS

Voltage Referenced to: V

= 0V, 0°C T

+70°C

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

OPERATING CURRENT CHARACTERISTICS

= 3.3V, 0°C T

+70°C

Version

Parameter

Symbol

Conditions

100/133

Units

Note

Operating Current
(One bank active)

CC1

Burst Length = 1
t

(min)

= 0mA

1080

Precharge Standby Current
in Power Down Mode

CC2

CKE

(max), t

= 10ns

Active Standby Current in
Power-Down Mode

CC3

CKE

(max), t

= 10ns

405

Operating Current (Burst mode)

CC4

Io = mA
Page burst
4 Banks activated
t

CCD

= 2CK

1125

Refresh Current

CC5

(min)

2205

Self Refresh Current

CC6

CKE

0.2V

Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

AC CHARACTERISTICS

75/10

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from CLK (pos. edge)

CL = 3

AC(3)

5.4

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

2.7

Data-out hold time (no load)

OHN

1.8

ACTIVE to PRECHARGE command

RAS

120K

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows)

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK +

7ns

1 CLK +

7ns

14, 25

Exit SELF REFRESH to ACTIVE command

XSR

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

AC FUNCTIONAL CHARACTERISTICS

PARAMETER

SYMBOL

75/10

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH
command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

Notes
1. All voltages referenced to V

2. This parameter is sampled. V

, V

CCQ

= +3.3V; = 25°C; pin under test biased at

1.4V. f = 1 MHz, TA

3. I

is dependent on output loading and cycle rates.Specifi ed values are obtained

with mini-mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper

operation over the full temperature range (0°C 70°C) is T

ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO

REFRESH commands, before proper device operation is ensured. (V

and V

CCQ

must be powered up simultaneously. V

and V

SSQ

must be at same potential.) The

two AUTO REFRESH command wake-ups should be repeated any time the t

REF

refresh requirement is exceeded.

7. AC characteristics assume t

= 1ns.

8. In addition to meeting the transition rate specifi cation, the clock and CKE must transit

between V

and V

(or between V

and V

) in a mono-tonic manner.

9. Outputs measured at 1.5V with equivalent load:

50pF

10. t

defi nes the time at which the output achieves the open circuit condition; it is not a

reference to V

or V

. The last valid data element will meet t

before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V, with timing referenced to 1.5V

crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at V

(MAX) and V

(MIN) and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no more than once every two clocks and

are other-wise at valid VIH or VIL levels.

13. I

specifi cations are tested after the device is properly initialized.

14. Timing actually specifi ed by t

CKS

; clock(s) specifi ed as a reference only at minimum

cycle rate.

15. Timing actually specifi ed by t

plus t

; clock(s) specifi ed as a reference only at

minimum cycle rate.

16. Timing actually specifi ed by t

17. Required clocks are specifi ed by JEDEC functionality and are not dependent on any

timing parameter.

18. The I

current will increase or decrease in a proportional amount by the amount the

frequency is altered for the test condition.

19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on t

= 7.5ns for 75/10 and 7.

22. V

overshoot: V

(MAX) = V

CCQ

+ 2V for a pulse width 3ns, and the pulse width

cannot be greater than one third of the cycle rate. V

under-shoot: V

(MIN) = -2V

for a pulse width 3ns.

23. The clock frequency must remain constant (stable clock is defi ned as a signal cycling

within timing constraints specifi ed for the clock pin) during access or precharge
states (READ, WRITE, including t

, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget (t

) begins 7.5ns/7ns after

the fi rst clock delay, after the last WRITE is executed.

25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. t

for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.
29. For 75/10, CL = 3, t

= 7.5ns; For 7, CL = 2, t

= 7.5ns

30. CKE is HIGH during refresh command period t

RFC

(MIN) else CKE is LOW. The I

DD6

limit is actually a nominal value and does not result in a fail value.

W3DG7268V-AD1

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

October 2004
Rev. 2

PRELIMINARY

Note: For industrial temperature range product, add an "I" to the end of the part number.

Ordering Information

Speed

CAS Latency

Height*

W3DG7268V10AD1

100MHz

CL=2

27.94 (1.10") MAX

W3DG7268V7AD1

133MHz

CL=2

27.94 (1.10") MAX

W3DG7268V75AD1

133MHz

CL=3

27.94 (1.10") MAX

PACKAGE DIMENSIONS FOR AD1

3.99

(0.157)

2.01 (0.079 Min)

67.72

(2.661 Max)

32.79

(1.291)

4.60 (0.181)

1.50 (0.059)

28.2

(1.112)

23.14

(0.913)

19.99

(0.787)

27.94

(1.10)

Max

3.81

(0.150)

MAX.

0.99

(0.039)

(± 0.004)

WEDC

300

PACKAGE DIMENSIONS FOR AD1

* All Dimensions are in millimeters and (inches).

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W3DG7268V-AD1

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W3DG7268V-AD1