White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

W3E16M64S-XBX

November 2003 Rev. 2

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip's 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.

The 128 MB DDR SDRAM uses a double data rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2

n-prefetch architecture with an

interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128MB DDR SDRAM effectively consists of a single 2

n-bit

wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding

n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver. DQS is a

16Mx64 DDR SDRAM

Preliminary*

! High Frequency = 200, 250, 266MHz
! Package:

· 219 Plastic Ball Grid Array (PBGA), 21 x 25mm

! 2.5V ±0.2V core power supply
! 2.5V I/O (SSTL_2 compatible)
! Differential clock inputs (CLK and CLK)
! Commands entered on each positive CLK edge
! Internal pipelined double-data-rate (DDR) architecture;

two data accesses per clock cycle

! Programmable Burst length: 2,4 or 8
! Bidirectional data strobe (DQS) transmitted/received

with data, i.e., source-synchronous data capture (one

per byte)

! DQS edge-aligned with data for READs; center-aligned

with data for WRITEs

! DLL to align DQ and DQS transitions with CLK
! Four internal banks for concurrent operation
! Two data mask (DM) pins for masking write data
! Programmable IOL/IOH option
! Auto precharge option
! Auto Refresh and Self Refresh Modes
! Commercial, Industrial and Military Temperature Ranges
! Organized as 16M x 64
! Weight: W3E16M64S-XBX - 2 grams typical

FEATURES

! 50% SPACE SAVINGS
! Reduced part count
! Reduced I/O count

· 17% I/O Reduction

! Reduced trace lengths for lower parasitic capacitance
! Suitable for hi-reliability applications
! Laminate interposer for optimum TCE match
! Upgradeable to 32M x 64 density (contact factory for

information)

* This data sheet describes a product that is not qualified or characterized and is
subject to change without notice.

GENERAL DESCRIPTION

BENEFITS

TSOP

11.9

22.3

Monolithic Solution

Actual Size

W3E16M64S-XBX

Area

I/O

Count

4 x 265mm2 = 1060mm2

4 x 66 pins = 264 pins

525mm2

50%

219 Balls

17%

W3E16M64S-XBX

White Electronic Designs

TSOP

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

W3E16M64S-XBX

. 1 P

ONFIGURATION

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.

IEW

9 10

11 12 13 14 15 16

CAS0

CLK3

Vss

CLK

CKE1

CS2

CAS2

DQML0

WE0

RAS0

CKE3

CLK3

DQMH3

DQMH1

CLK1

RAS2

WE2

DQML2

Vss

DQMH0

CLK

CKE0

CS3

CAS3

WE3

DQML1

WE1

CKE2

CLK

DQMH2

DQSH3

DQSL3

CLK0

RAS3

DQML3

VREF

RAS1

CAS1

CLK2

DQSL2

DQSH2

A12

DQSH0

DNU

DQSL1

DNU

CCQ

DQSL0

DQSH1

Vss

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W3E16M64S-XBX

Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-12 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-

ing device initialization, register definition, command de-
scriptions and device operation.

DDR SDRAMs must be powered up and initialized in a pre-
defined manner. Operational procedures other than those
specified may result in undefined operation. Power must
first be applied to V

and V

CCQ

simultaneously, and then to

REF

(and to the system V

). V

must be applied after V

CCQ

to avoid device latch-up, which may cause permanent dam-
age to the device. V

REF

can be applied any time after V

CCQ

but is expected to be nominally coincident with V

. Except

for CKE, inputs are not recognized as valid until after V

REF

applied. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V

is applied. Maintaining an LVCMOS LOW

level on CKE during power-up is required to ensure that the
DQ and DQS outputs will be in the High-Z state, where they
will remain until driven in normal operation (by a read ac-
cess). After all power supply and reference voltages are
stable, and the clock is stable, the DDR SDRAM requires a
200

µs delay prior to applying an executable command.

Once the 200

µs delay has been satisfied, a DESELECT or

NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE
ALL command should be applied. Next a LOAD MODE REG-
ISTER command should be issued for the extended mode
register (BA1 LOW and BA0 HIGH) to enable the DLL, fol-
lowed by another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL and to
program the operating parameters. Two-hundred clock
cycles are required between the DLL reset and any READ
command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be
performed (t

RFC

must be satisfied.) Additionally, a LOAD

MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating param-
eters without resetting the DLL) is required. Following these
requirements, the DDR SDRAM is ready for normal operation.

The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the

INITIALIZATION

strobe transmitted by the DDR SDRAM during READs and by
the memory contoller during WRITEs. DQS is edge-aligned
with data for READs and center-aligned with data for WRITEs.
Each chip has two data strobes, one for the lower byte and
one for the upper byte.

The 128MB DDR SDRAM operates from a differential clock (CLK and
CLK); the crossing of CLK going HIGH and CLK going LOW will be
referred to as the positive edge of CLK. Commands (address and
control signals) are registered at every positive edge of CLK. Input
data is registered on both edges of DQS, and output data is refer-
enced to both edges of DQS, as well as to both edges of CLK.

Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with
the READ or WRITE command are used to select the bank
and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.

The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-
saving power-down mode.

FUNCTIONAL DESCRIPTION

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W3E16M64S-XBX

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

SPEED

LATENCY = 2

LATENCY = 2.5

-200

100

-250

100

125

-266

100

133

selection of a burst length, a burst type, a CAS latency, and
an operating mode, as shown in Figure 3. The Mode Regis-
ter is programmed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. (Except for bit A8 which is self clearing).

Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller must wait
the specified time before initiating the subsequent opera-
tion. Violating either of these requirements will result in un-
specified operation.

Mode register bits A0-A2 specify the burst length, A3 speci-
fies the type of burst (sequential or interleaved), A4-A6 specify
the CAS latency, and A7-A12 specify the operating mode.

Read and write accesses to the DDR SDRAM are burst ori-
ented, with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum num-
ber of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4 or 8 loca-
tions are available for both the sequential and the inter-
leaved burst types.

Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length is
set to four (where Ai is the most significant column address
for a given configuration); and by A3-Ai when the burst
length is set to eight. The remaining (least significant) ad-
dress bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both
READ and WRITE bursts.

BURST LENGTH

The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
bit of output data. The latency can be set to 2 or 2.5 clocks.

If a READ command is registered at clock edge

n, and the

latency is

m clocks, the data will be available by clock edge

n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.

Reserved states should not be used as unknown operation
or incompatibility with future versions may result.

BURST TYPE

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.

READ LATENCY

ABLE

2 - C

ATENCY

OPERATING MODE

The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with
bits A7 and A9-A12 each set to zero, bit A8 set to one, and
bits A0-A6 set to the desired values. Although not required,
JEDEC specifications recommend when a LOAD MODE REG-
ISTER command is issued to reset the DLL, it should always
be followed by a LOAD MODE REGISTER command to se-
lect normal operating mode.

All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.

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W3E16M64S-XBX

The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength, and
QFC. These functions are controlled via the bits shown in
Figure 5. The extended mode register is programmed via
the LOAD MODE REGISTER command to the mode register
(with BA0 = 1 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. The enabling of the DLL should always be followed
by a LOAD MODE REGISTER command to the mode register
(BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subse-
quent operation. Violating either of these requirements
could result in unspecified operation.

EXTENDED MODE REGISTER

ABLE

1 - B

URST

EFINITION

Burst Starting Column

Order of Accesses Within a Burst

Length

Address

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Type = Sequential Type = Interleaved

NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects
the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select
the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2
select the starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.

. 3 M

ODE

EGISTER

EFINITION

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Operating Mode

* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs.

the

extended

mode

Reserved

M10

M11

M12

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W3E16M64S-XBX

The DESELECT function (CS HiGH) prevents new commands
from being executed by the DDR SDRAM. The SDRAM is
effectively deselected. Operations already in progress are
not affected.

The NO OPERATION (NOP) command is used to perform a
NOP to the selected DDR SDRAM (CS is LOW). This prevents
unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.

The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until t

MRD

is met.

COMMAND READ

NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQS

T0 T1 T2

T2n

T3n

COMMAND READ

NOP

CL = 2

DQS

CLK

T0 T1 T2

T2n

T3n

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

DATA

CLK

The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM suppor ts an option for
reduced drive. This option is intended for the suppor t of
the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.

The DLL must be enabled for normal operation. DLL enable
is required during power-up initialization and upon return-
ing to normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device exits
self refresh mode, the DLL is enabled automatically.) Any
time the DLL is enabled, 200 clock cycles must occur be-
fore a READ command can be issued.

. 4 C

ATENCY

. 5 E

XTENDED

ODE

EGISTER

EFINITION

OUTPUT DRIVE STRENGTH

DLL ENABLE/DISABLE

The Tr uth Table provides a quick reference of available
commands. This is followed by a written description of
each command.

COMMANDS

NO OPERATION (NOP)

DESELECT

LOAD MODE REGISTER

DLL

Enable

Disable

DLL

Extended Mode
Register (Ex)

Address Bus

Operating Mode

QFC

Drive Strength

Normal

Reduced

QFC Function

Disabled

Reserved

E22

Operating Mode

Reserved

E2, E1, E0

Valid

E12

E10

E11

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE function is not supported.

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W3E16M64S-XBX

The WRITE command is used to initiate a burst write access to
an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-8 selects the
starting column location. The value on input A10 determines
whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE
is selected, the row being accessed will be precharged at the
end of the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Input data
appearing on the D/Qs is written to the memory array subject
to the DQM input logic level appearing coincident with the
data. If a given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal is regis-
tered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.

WRITE

RUTH

ABLE

- C

OMMANDS

OTE

NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for
WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.

ACTIVE

READ

The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0-12 selects the row. This row remains
active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.

The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 se-
lects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO

NAME (FUNCTION)

RAS

CAS

ADDR

DESELECT (NOP) (9)

NO OPERATION (NOP) (9)

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

Bank/Col

BURST TERMINATE (8)

PRECHARGE (Deactivate row in bank or banks) ( 5)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

Op-Code

RUTH

ABLE

- DM O

PERATION

NAME (FUNCTION)

DQs

WRITE ENABLE (10)

Valid

WRITE INHIBIT (10)

PRECHARGE is not selected, the row will remain open for
subsequent accesses.

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W3E16M64S-XBX

The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (t

) after the PRECHARGE command is is-

sued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in
the current bank and does not violate any other timing pa-
rameters. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as "Don't Care." Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
A PRECHARGE command will be treated as a NOP if there is
no open row in that bank (idle state), or if the previously
open row is already in the process of precharging.

AUTO PRECHARGE is a feature which performs the same indi-
vidual-bank PRECHARGE function described above, but without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled or dis-
abled for each individual READ or WRITE command. The device
supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. This "earliest valid stage" is
determined as if an explicit precharge command was is-
sued at the earliest possible time, without violating t

RAS

(MIN).The user must not issue another command to the same
bank until the precharge time (t

) is completed. This is deter-

mined as if an explicit PRECHARGE command was issued at
the earliest possible time, without violating t

RAS

(MIN).

The BURST TERMINATE command is used to truncate READ
bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE
command will be truncated. The open page which the READ
burst was terminated from remains open.

PRECHARGE

AUTO PRECHARGE

AUTO REFRESH is used during normal operation of the DDR
SDRAM and is analogous to CAS-BEFORE-RAS (CBR) RE-
FRESH in conventional DRAMs. This command is nonpersis-
tent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh control-
ler. This makes the address bits "Don't Care" during an AUTO
REFRESH command. Each DDR SDRAM requires AUTO RE-
FRESH cycles at an average interval of 7.8125

µs (maximum).

To allow for improved efficiency in scheduling and switch-
ing between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, mean-
ing that the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command
is 9 x 7.8125

µs (70.3µs). This maximum absolute interval is

to allow future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, without
allowing excessive drift in t

between updates.

Although not a JEDEC requirement, to provide for future func-
tionality features, CKE must be active (High) during the AUTO
REFRESH period. The AUTO REFRESH period begins when the
AUTO REFRESH command is registered and ends t

RFC

later.

The SELF REFRESH command can be used to retain data in
the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM re-
tains data without external clocking. The SELF REFRESH com-
mand is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). The DLL is automatically disabled
upon entering SELF REFRESH and is automatically enabled
upon exiting SELF REFRESH (200 clock cycles must then
occur before a READ command can be issued). Input sig-
nals except CKE are "Don't Care" during SELF REFRESH.

The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable prior to CKE going back
HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for t

XSNR

, because time is required for the

completion of any internal refresh in progress.

A simple algorithm for meeting both refresh and DLL re-
quirements is to apply NOPs for 200 clock cycles before
applying any other command.

* Self refresh available in commercial and industrial temperatures only.

AUTO REFRESH

SELF REFRESH*

BURST TERMINATE

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W3E16M64S-XBX

BSOLUTE

AXIMUM

ATINGS

Parameter

Unit

Voltage on V

, V

CCQ

Supply relative to Vss

-1 to 3.6

Voltage on I/O pins relative to Vss

-1 to 3.6

Operating Temperature T

(Mil)

-55 to +125

°C

Operating Temperature T

(Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +150

°C

NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

APACITANCE

OTE

13)

Parameter

Symbol

Max

Unit

Input Capacitance: CLK

Addresses, BA

0-1

Input Capacitance

Input Capacitance: All other input-only pins

Input/Output Capacitance: I/Os

Description

Symbol Max Units Notes

Junction to Ambient

Theta JA

14.5

C/W

(No Airflow)

Junction to Ball

Theta JB

10.0

C/W

Junction to Case (Top)

Theta JC

5.4

C/W

BGA T

HERMAL

ESISTANCE

NOTE 1:
Refer to AN #0001 at www.whiteedc.com in the
application notes section for modeling conditions.

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W3E16M64S-XBX

250MHz

Parameter/Condition

Symbol

266MHz 200MHz

Units

OPERATING CURRENT: One bank; Active-Precharge; t

= t

(MIN); t

= t

(MIN); DQ, DM, and DQS inputs

C C 0

480

460

changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; t

= t

(MIN); t

= t

(MIN);

C C 1

660

520

IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; t

= t

(MIN);

CC2P

CKE = LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; t

= t

(MIN); CKE = HIGH; Address and other control

C C 2 F

160

inputs changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM (51)

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; t

= t

(MIN);

CC3P

120

100

CKE = LOW (23, 32, 50)
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; t

= t

RAS

(MAX);

CC3N

180

160

= t

(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control

inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs

CC4R

1,000

860

changing once per clock cycle; t

= t

(MIN); I

OUT

= 0mA (22, 48)

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs

C C 4 W

1,000

760

changing once per clock cycle; t

= t

(MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)

AUTO REFRESH CURRENT

= t

(MIN) (27, 50)

C C 5

980

860

= 7.8125µs (27, 50)

C C 5 A

SELF REFRESH CURRENT: CKE

0.2V

Standard (11)

C C 6

OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, t

(MIN); t

= t

(MIN);

C C 7

1600

1500

Address and control inputs change only during Active READ or WRITE commands. (22, 49)

Parameter/Condition

Symbol

Units

Min

Max

Supply Voltage

2.3

2.7

I/O Supply Voltage

CCQ

2.3

2.7

Input High Voltage: Logic 1; All inputs (21)

REF

- 0.04

REF

+ 0.04

Input Low Voltage: Logic 0; All inputs (21)

-0.3

REF

- 0.15

Input Leakage Current: Any input 0V

(All other pins not under test = 0V)

-2

µA

Input Leakage Address Current (All other pins not under test = 0V)

-8

µA

Output Leakage Current: I/Os are disabled; 0V

OUT

-5

µA

Output Levels: Full drive option
High Current (V

OUT

= V

CCQ

- 0.373V, minimum V

REF,

minimum V

)

-16.8

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

16.8

Output Levels: Reduced drive option
High Current (V

OUT

= V

CCQ

- 0.763V, minimum V

REF,

minimum V

)

OHR

-9

Low Current (V

OUT

= 0.763V, maximum V

REF

, maximum V

)

OLR

I/O Reference Voltage

REF

0.49 x V

CCQ

0.51 x V

CCQ

I/O Termination Voltage

REF

- 0.04

REF

+ 0.04

DC E

LECTRICAL

HARACTERISTICS

PERATING

ONDITIONS

OTES

1, 6)

= +2.5V ±0.2V; T

= -55°C

+125°C)

PECIFICATIONS

ONDITIONS

OTES

1-5, 10, 12, 14)

= +2.5V ±0.2V; T

= -55°C

+125°C)

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

W3E16M64S-XBX

266 MHz CL 2.5

250 MHz CL2.5

200 MHz CL2.5

200 CL 2

200 MHz CL2

150 MHz CL2

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Access window of DQs from CLK/CLK

-0.75

+0.75

-0.8

+0.8

-0.8

+0.8

CLK high-level width (30)

0.45

0.55

0.45

0.55

0.45

0.55

CLK low-level width (30)

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5 (45, 52)

(2.5)

7.5

CL = 2 (45, 52)

(2)

DQ and DM input hold time relative to DQS (26, 31)

0.5

0.6

DQ and DM input setup time relative to DQS (26, 31)

0.5

0.6

DQ and DM input pulse width (for each input) (31)

DIPW

1.75

Access window of DQS from CLK/CLK

DQSCK

-0.75

+0.75

-0.8

+0.8

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)

DQSQ

0.5

0.6

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CLK rising - setup time

DSS

0.2

DQS falling edge from CLK rising - hold time

DSH

0.2

Half clock period (34)

Data-out high-impedance window from CLK/CLK (18, 42)

+0.75

+0.8

Data-out low-impedance window from CLK/CLK (18, 43)

-0.75

-0.8

Address and control input hold time (fast slew rate) (14)

IHF

0.90

1.1

Address and control input setup time (fast slew rate) (14)

ISF

0.90

1.1

Address and control input hold time (slow slew rate) (14)

IHS

1.1

Address and control input setup time (slow slew rate) (14)

ISS

1.1

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)

-t

QHS

-t

QHS

-t

QHS

Data hold skew factor

QHS

0.75

ACTIVE to PRECHARGE command (35)

RAS

120,000

ACTIVE to READ with Auto precharge command (46)

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period (50)

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble (42)

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time (20, 21)

WPRES

DQS write postamble (19)

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (25)

- t

DQSQ

- t

DQSQ

- t

DQSQ

REFRESH to REFRESH command interval (23)

REFC

70.3

µs

Average periodic refresh interval (23)

REFI

7.8

µs

Terminating voltage delay to VDD

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

LECTRICAL

HARACTERISTICS

ECOMMENDED

AC O

PERATING

HARACTERISTICS

OTES

1-5, 14-17, 33)

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

W3E16M64S-XBX

NOTES:
1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage
range specified.
3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test

environment, but input timing is still referenced to V

REF

(or to the crossing point for

CLK/CLK), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between V

(AC) and V

(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. V

REF

is expected to equal V

CCQ

/2 of the transmitting device and to track

variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on V

REF

may not exceed ±2 percent of the DC value. Thus, from V

CCQ

/2,

REF

is allowed ±25mV for DC error and an additional ±25mV for AC noise. This

measurement is to be taken at the nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. V

is the magnitude of the difference between the input level on CLK and the

input level on CLK.
9. The value of V

and V

are expected to equal V

CCQ

/2 of the transmitting

device and must track variations in the DC level of the same.
10. I

is dependent on output loading and cycle rates. Specified values are

obtained with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. I

specifications are tested after the device is properly initialized, and is

averaged at the defined cycle rate.
13. This parameter is not tested but guaranteed by design. t

= 25°C, F= 1 MHz

14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates
1V/ns and faster, t

and t

are reduced to 900ps. If the slew rate is less than 0.5V/

ns, timing must be derated: t

has an additional 50ps per each 100mV/ns

reduction in slew rate from the 500mV/ns. t

has 0ps added, that is, it remains

constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CLK/CLK input reference level (for timing referenced to CLK/CLK) is the point at
which CLK and CLK cross; the input reference level for signals other than CLK/CLK is V

REF.

16. Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the

period before V

REF

stabilizes, CKE

0.3 x V

CCQ

is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is V

TT.

18. t

and t

transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will
operate with a greater value for this parameter, but system performance (bus
turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies
when no WRITEs were previously in progress on the bus. If a previous WRITE was
in progress, DQS could be HIGH during this time, depending on t

DQSS

22. MIN (t

or t

RFC)

for I

measurements is the smallest multiple of t

that meets

the minimum absolute value for the respective parameter. t

RAS

(MAX) for I

measurements is the largest multiple of t

that meets the maximum absolute

value for t

RAS

23. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
25. The valid data window is derived by achieving other specifications - tHP
(t

/2), t

DQSQ

, and t

= t

- t

QHS

). The data valid window derates directly

porportional with the clock duty cycle and a practical data valid window can
be derived. The clock is allowed a maximum duty cycle variation of 45/55.
Functionality is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging between
50/50 and 45/55.
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (t

RFC

[MIN]) else CKE is LOW (i.e., during standby).

160

140

120

100

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

Reference

Point

30pF

Output
(V

OUT

)

ULL

-D

OWN

HARACTERISTICS

. B P

ULL

-U

HARACTERISTICS

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

CCQ -

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

W3E16M64S-XBX

28. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through to the target
AC level, V

(AC) or V

(AC).

b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target
DC level, V

(DC) or V

(DC).

29. The Input capacitance per pin group will not differ by more than this
maximum amount for any given device.
30. CLK and CLK input slew rate must be

1V/ns (2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If
the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must
be added to t

and t

for each 100mV/ns reduction in slew rate. If slew rate

exceeds 4V/ns, functionality is uncertain.
32. V

must not vary more than 4% if CKE is not active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is
allowed to vary by the same amount.
34. t

min is the lesser of t

minimum and t

minimum actually applied to the

device CLK and CLK inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
t

RAS

(MIN) can be satisfied prior to the internal precharge command being issued.

36. Any positive glitch must be less than 1/3 of the clock and not more than
+400mV or 2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is
more positive.
37. Normal Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure B.
d)The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-
down current should be between .71 and 1.4, for device drain-to-source
voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure C.

b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure D.
d)The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-
down current should be between .71 and 1.4, for device drain-to-source
voltages from 0.1V to 1.0 V, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current
should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from a minimum V

level and the

referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
40. V

overshoot: V

(MAX) = V

CCQ

+1.5V for a pulse width

3ns and

the pulse width can not be greater than 1/3 of the cycle rate.
41. V

and V

CCQ

must track each other.

42. This maximum value is derived from the referenced test load. In practice, the
values obtained in a typical terminated design may reflect up to 310ps less for
t

(MAX) and the last DVW. t

(MAX) will prevail over t

DQSCK

(MAX) + t

RPST

(MAX)

condition. t

(MIN) will prevail over t

DQSCK

(MIN) + t

RPRE

(MAX) condition.

43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.
44. During initialization, V

CCQ

, V

TT,

and V

REF

must be equal to or less than V

0.3V. Alternatively, V

may be 1.35V maximum during power up, even if V

CCQ

are 0 volts, provided a minimum of 42 ohms of series resistance is used

between the V

supply and the input pin.

45. The current part operates below the slowest JEDEC operating frequency of
83 MHz. As such, future die may not reflect this option.
46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is
executed. That is, from the time the AUTO REFRESH command is registered, CKE
must be active at each rising clock edge, until t

RFC

has been satisfied.

51. I

CC2N

specifies the DQ, DQS, and DM to be driven to a valid high or low logic

level. I

CC2Q

is similar to I

CC2F

except I

CC2Q

specifies the address and control inputs

to remain stable. Although I

CC2F

, I

CC2N

, and I

CC2Q

are similar, I

CC2F

is "worst case."

52. Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset. This is followed by 200 clock cycles before any READ
command.

. C P

ULL

-D

OWN

HARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

. D P

ULL

-U

HARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

CCQ -

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

-10

-20

-30

-40

-50

-60

-70

-80

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