W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

32Mx72 DDR SDRAM

FEATURES

Data rate = 200, 250, 266, 333Mbs

Package:

· 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

2.5V ±0.2V core power supply

2.5V I/O (SSTL_2 compatible)

Differential clock in puts (CK and CK#)

Commands entered on each positive CK edge

Internal pipelined double-data-rate (DDR)
ar chi tec ture; two data accesses per clock cy cle

Programmable Burst length: 2,4 or 8

Bidirectional data strobe (DQS) transmitted/
re ceived with data, i.e., source-syn chro nous data
capture (one per byte)

DQS edge-aligned with data for READs; center-
aligned with data for WRITEs

DLL to align DQ and DQS transitions with CK

Four internal banks for concurrent operation

Data mask (DM) pins for masking write data
(one per byte)

Programmable

IOL/IOH

option

Auto precharge option

Auto Refresh and Self Refresh Modes

Commercial, Industrial and Military
TemperatureRang es

Organized as 32M x 72

Weight: W3E32M72S-XSBX - 2.5 grams typical

* This product is subject to change without notice.

BENEFITS

73%

Space

Savings

vs.

TSOP

· 44% Space Savings vs FPBGA

duced part count

37% I/O reduction vs TSOP

· 31% I/O reduction vs FPBGA

Reduced trace lengths for lower parasitic
capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

Upgradeable to 64M x 72 density (con tact fac to ry
for information)

GENERAL DESCRIPTION

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dy nam ic ran dom-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate
ar chi tec ture to achieve high-speed operation. The
double data rate ar chi tec ture is essentially a 2n-prefetch
architecture with an in ter face designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two cor re spond ing n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.

A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.

The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Com mands (ad dress and control signals) are registered
at every positive edge of CK. Input data is registered on
both edg es of DQS, and out put data is ref er enced to both
edges of DQS, as well as to both edges of CK.

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

DENSITY COMPARISONS

Read and write accesses to the DDR SDRAM are burst
ori ent ed; accesses start at a selected location and continue
for a pro grammed number of locations in a programmed
sequence. Accesses begin with the registration of an
AC TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The ad dress bits registered
coincident with the READ or WRITE com mand are used
to select the bank and the starting column location for the
burst access.

The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge func tion may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.

The pipelined, multibank architecture of DDR SDRAMs al lows
for concurrent operation, thereby providing high ef fec tive
band width by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-

Area

5 x 265mm

= 1325mm

352mm

73%

5 x 66 pins = 330 pins

208 Balls

37%

S
A
V

N
G
S

I/O

Count

TSOP Approach (mm)

22.3

11.9

66
TSOP

11.9

66
TSOP

11.9

66
TSOP

11.9

66
TSOP

Area

5 x 125mm

= 625mm

352mm

44%

5 x 60 balls = 300 balls

208 Balls

31%

S
A
V

N
G
S

I/O

Count

CSP Approach (mm)

60
FBGA

10.0

60
FBGA

10.0

60
FBGA

10.0

60
FBGA

10.0

12.5

11.9

66
TSOP

60
FBGA

10.0

Actual Size

W3E32M72S-XSBX

Actual Size

W3E32M72S-XSBX

saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.

FUNCTIONAL DE SCRIP TION

Read and write accesses to the DDR SDRAM are burst
ori ent ed; accesses start at a selected location and continue
for a pro grammed number of locations in a pro grammed
se quence. Ac cess es begin with the registration of an
AC TIVE com mand which is then followed by a READ or
WRITE com mand. The address bits registered coincident
with the AC TIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE com mand are used to select the
start ing column location for the burst access.

Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information cov er ing device initialization, register defi nition,
command de scrip tions and de vice operation.

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

FIG. 1 PIN CONFIGURATION

NOTE: DNU = Do Not Use.

IEW

1 2 3 4 5 6 7 8 9 10 11

VCCQ

VSS

DQMH2

DQ41

DQ44

DQ64

DNU

VCCQ

VSS

VCC

DQ71

WE4#

DQ22

DQ23

DQSL1

VSS

VCCQ

VSS

VCC

VSS

CK0

DQMH0

DQ9

DQ11

DQ65

DQ66

A12

A10

DQ70

CAS4#

DQ52

DQ54

DQSL3

CAS3

VSS

VCC

VSS

CS2

CK2

DQSH2

DQ10

DQ13

DQ15

DQ69

BA1

BA0

DQSL4

RAS4#

DQ18

DQ21

DQ55

WE3#

CAS1#

VSS

VCCQ

CS0

CK0

DQSH0

DQ42

DQ45

DQ47

DNU

VCCQ

DQML4

DQ16

DQ50

DQ19

DQ53

WE1#

RAS3#

VCCQ

CKE2

CK2

DQ8

DQ43

DQ14

DQ46

DQ67

VCC

VSS

VCCQ

DQ68

DQ48

DQ17

DQ51

DQ20

DQML3

RAS1#

VCCQ

CAS2

DQML2

DQ5

DQ3

DQ1

DQ32

DQ72

VCCQ

VSS

VCC

DQSH4

DQ63

DQ30

DQ28

DQ24

CK1

CKE3

VCCQ

VCC

VSS

WE2

DQSL2

DQ38

DQ37

DQ79

DQ75

DNU*

A11

CK4

CKE4

DQ59

DQ57

DQSH1

CK3

VSS

VCC

VCCQ

RAS0

CAS0

DQ39

DQ36

DQ34

DQ0

DQ73

VCCQ

DQMH4

DQ31

DQ61

DQ58

DQMH3

CK3

CS1

VCCQ

VSS

RAS2

WE0

DQ7

DQ4

DQ2

DQ77

DQ74

CK4#

DQ62

DQ29

DQ26

DQMH1

CK1

CS3

VSS

CKE0

DQML0

DQ40

DQ12

DQ33

VSS

VCC

VSS

VREF

VSS

VCC

VSS

DQ49

DQ60

DQ56

DQML1

CKE1

VSS

VCCQ

VSS

DQSL0

DQ6

DQ35

DQ78

DQ76

VCC

VSS

VCCQ

DNU

CS4#

DQ27

DQ25

DQSH3

VSS

VCCQ

VSS

* pin J10 is reserved for signal A13 on future upgrades.

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

0-12

0-1

CAS

CKE

DQML

DQMH

RAS

CAS

RAS

0-12

0-1

CAS

RAS

CAS

RAS

CKE

DQML

DQMH

RAS

CAS

RAS

0-12

0-1

CAS

CKE

DQML

DQMH

RAS

CAS

RAS

0-12

0-1

CAS

CKE

DQSL

DQSH

REF

DQSL

DQSH

REF

DQSL

DQSH

REF

DQSL

DQSH

REF

DQML

DQMH

RAS

CAS

RAS

0-12

0-1

CAS

CKE

DQSL

DQSH

REF

DQML

DQMH

FIG. 2 FUNCTIONAL BLOCK DIAGRAM

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a
pre defi ned manner. Operational procedures other than
those specifi ed may result in undefi ned operation. Power
must fi rst be applied to V

and V

CCQ

simultaneously, and

then to V

REF

(and to the system V

). V

must be applied

after V

CCQ

to avoid device latch-up, which may cause

per ma nent dam age to the device. V

REF

can be applied any

time after V

CCQ

but is expected to be nominally coincident

with V

. Except for CKE, inputs are not recognized as

valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after V

applied. After CKE passes through V

, it will transition to

an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read ac cess). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable com mand.

Once the 200µs delay has been satisfi ed, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REG IS TER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the D

, fol lowed by another LOAD MODE

and to program the operating

parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must
be performed (t

RFC

must be satisfi ed.) Additionally, a LOAD

MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa ram e ters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal op er a tion.

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to defi ne the specifi c mode of
op er a tion of the DDR SDRAM. This defi nition includes the
selection of a burst length, a burst type, a CAS latency,
and an op er at ing mode, as shown in Figure 3. The Mode
Reg is ter is programmed via the MODE REG IS TER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored in for ma tion until it is pro grammed again or
the device loses power. (Ex cept for bit A8 which is self
clearing).

Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Reg is ter must be load ed (reloaded) when all banks are
idle and no bursts are in progress, and the con trol ler must
wait the spec i fi ed time be fore ini ti at ing the sub se quent
op er a tion. Vi o lat ing either of these re quire ments will result
in un spec i fi ed operation.

Mode register bits A0-A2 specify the burst length, A3
spec i fi es the type of burst (sequential or in ter leaved),
A4-A6 spec i fy the CAS latency, and A7-A12 specify the
op er at ing mode.

BURST LENGTH

Read and write ac cess es to the DDR SDRAM are burst
ori ent ed, with the burst length being programmable,
as shown in Fig ure 3. The burst length determines
the maximum num ber of column lo ca tions that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 lo ca tions are avail able for both the
sequential and the in ter leaved burst types.

Reserved states should not be used, as unknown op er a tion
or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
col umns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
mean ing that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most signifi cant
column address for a given confi guration); and by A3-Ai
when the burst length is set to eight. The remaining (least
sig nifi cant) ad dress bit(s) is (are) used to select the starting
lo ca tion within the block. The pro grammed burst length
ap plies to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be pro grammed to be
either se quen tial or interleaved; this is re ferred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is de ter mined by
the burst length, the burst type and the start ing column
address, as shown in Table 1.

READ LATENCY

The READ latency is the delay, in clock cycles, between
the reg is tra tion of a READ command and the avail abil i ty
of the fi rst bit of output data. The latency can be set to 2
or 2.5 clocks.

If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the op er at ing fre quen cies at
which each CAS latency setting can be used.

Reserved states should not be used as unknown operation
or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
re quired, JEDEC specifi cations recommend when a LOAD
MODE REG IS TER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to se lect nor mal op er at ing mode.

All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specifi ed time before initiating
any sub se quent operation. Violating either of these
requirements could result in unspecifi ed operation.

OUTPUT DRIVE STRENGTH

The normal full drive strength for all outputs are specifi ed to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.

DLL ENABLE/DISABLE

When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon re turn ing to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur be fore a READ
command can be issued.

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED

CAS

LATENCY = 2

CAS

LATENCY = 2.5

-200

100

-250

100

125

-266

100

133

-333

166

TABLE 2 - CAS LATENCY

COMMANDS

The Truth Table provides a quick reference of available
com mands. This is followed by a written de scrip tion of
each command.

DESELECT

The DESELECT function (CS# High) prevents new
com mands from be ing ex e cut ed by the DDR SDRAM.
The SDRAM is ef fec tive ly de se lect ed. Op er a tions already
in progress are not af fect ed.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
com mand cannot be issued until t

MRD

is met.

ACTIVE

The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs se lects the bank, and the
address pro vid ed on inputs A0-12 selects the row. This row
remains active (or open) for ac cess es until a PRECHARGE
com mand is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.

READ

The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input
A10 de ter mines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent ac cess es.

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

TABLE 1 - BURST DEFINITION

Burst

Length

Starting Column

Address

Order of Accesses With in a Burst

Type = Sequential

Type = In ter leaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0

selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1

select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

FIG. 3 MODE REGISTER DEFINITION

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Operating Mode

* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode

Reserved

M10

M11

M12

12 11 10

WRITE

The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input A10
de ter mines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open
for sub se quent accesses. Input data appearing on the DQ
is written to the memory array subject to the DQM input
logic level ap pear ing co in ci dent with the data. If a given
DQM signal is reg is tered LOW, the cor re spond ing data
will be written to mem o ry; if the DQM signal is reg is tered
HIGH, the cor re spond ing data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (t

) after the PRECHARGE command is

is sued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
pa ram e ters. Input A10 de ter mines wheth er one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, in puts BA0, BA1 select the
bank. Oth er wise BA0, BA1 are treated as "Don't Care."
Once a bank has been precharged, it is in the idle state and

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

COMMAND

READ

NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQS

T2n

T3n

COMMAND

READ

NOP

CL = 2

DQS

CLK

T2n

T3n

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

DATA

CLK

FIG. 4 CAS LATENCY

FIG. 5 EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

Extended Mode
Register (Ex)

Address Bus

Operating Mode

Drive Strength

Normal

Reduced

Operating Mode

Reserved

E1, E0

Valid

E12

E10

E11

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.

14 13 12 11 10

DLL

must be ac ti vat ed pri or to any READ or WRITE commands
being is sued to that bank. A PRECHARGE com mand will
be treat ed as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
pro cess of precharging.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the
same in di vid u al-bank PRECHARGE function de scribed
above, but with out re quir ing an explicit command. This is
ac com plished by using A10 to enable AUTO PRECHARGE
in conjunction with a spe cifi c READ or WRITE command.
A precharge of the bank/row that is ad dressed with the
READ or WRITE com mand is au to mat i cal ly performed
upon com ple tion of the READ or WRITE burst. AUTO
PRECHARGE is non per sis tent in that it is either en abled
or dis abled for each in di vid u al READ or WRITE command.
The device sup ports concurrent auto precharge if the
com mand to the oth er bank does not in ter rupt the data
transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This

"earliest valid stage" is determined as if an explicit
precharge command was is sued at the earliest possible
time, without violating t

RAS

(MIN).The user must not is sue

an oth er com mand to the same bank until the precharge
time (t

) is com plet ed.

BURST TERMINATE

The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.

AUTO REFRESH

AUTO REFRESH is used during normal op er a tion of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) RE FRESH in con ven tion al DRAMs. This com mand
is non per sis tent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.

The addressing is generated by the internal refresh
con trol ler. This makes the address bits "Don't Care"

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NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2.

A0-12 defi ne the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).

A0-12 provide row address, and BA0, BA1 provide bank address.

A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.

A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are "Don't Care."

TRUTH TABLE - COMMANDS (NOTE 1)

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

DESELECT (NOP) (9)

H X X X

NO OPERATION (NOP) (9)

H X

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

Bank/Col

BURST TERMINATE (8)

L X

PRECHARGE (Deactivate row in bank or banks) ( 5)

L Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

H X

LOAD MODE REGISTER (2)

L Op-Code

TRUTH TABLE - DM OPERATION

NAME (FUNCTION)

DQs

WRITE ENABLE (10)

Valid

WRITE INHIBIT (10)

H X

This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.

Internal refresh counter controls row addressing; all inputs and I/Os are "Don't
Care" except for CKE.

Applies only to read bursts with auto precharge disabled; this command is
undefi ned (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.

DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

during an AUTO RE FRESH command. Each DDR SDRAM
requires AUTO RE FRESH cycles at an average interval
of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and
switch ing between tasks, some fl exibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, mean ing that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in t

between updates.

Although not a JEDEC requirement, to provide for future
func tion al ity features, CKE must be active (High) during
the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered
and ends t

RFC

later.

SELF REFRESH*

The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM re tains data with out external clocking. The SELF
RE FRESH com mand is ini ti at ed like an AUTO REFRESH
com mand except CKE is dis abled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH and
is automatically enabled upon exiting SELF REFRESH (A
DLL reset and 200 clock cycles must then oc cur before a
READ command can be issued). Input sig nals except CKE
are "Don't Care" during SELF REFRESH. VREF voltage is
also required for the full duration of SELF REFRESH.

The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands is sued for t

XSNR

be cause time is required for the com ple tion of any internal
refresh in progress.

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A simple algorithm for meeting both refresh and DLL
re quire ments is to apply NOPs for t

XSNR

time, then a DLL

Reset and NOPs for 200 additional clock cycles before
applying any other command.

* Self refresh available in commercial and industrial temperatures only.

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

Voltage on V

, V

CCQ

Supply relative to Vss

-1 to 3.6

Voltage on I/O pins relative to Vss

-0.5V to V

CCQ

+0.5V

Operating Temperature T

(Mil)

-55 to +125

°C

Operating Temperature T

(Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +125

°C

Maximum Junction Temperature

125

°C

NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage

to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other
conditions greater than those in di cat ed in the operational sections of this specifi cation is not implied.
Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.

CAPACITANCE (NOTE 13)

Parameter

Symbol

Max

Unit

Input Capacitance: CK/CK#

Addresses, BA

0-1

Input Capacitance

Input Capacitance: All other input-only pins

Input/Output Capacitance: I/Os

BGA THERMAL RESISTANCE

Description

Symbol

Max

Units

Notes

Junction to Ambient (No Airfl ow)

Theta JA

13.7

°C/W

Junction to Ball

Theta JB

10.3

°C/W

Junction to Case (Top)

Theta JC

4.6

°C/W

Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.wedc.com in the application notes
section for modeling conditions.

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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)

, V

CCQ

= +2.5V ± 0.2V; -55°C

+125°C

Parameter/Condition

Symbol

Min

Max

Units

Supply Voltage (36, 41)

2.3

2.7

I/O Supply Voltage (36, 41, 44)

CCQ

2.3

2.7

Input Leakage Current: Any input 0V V

(All other pins not under test = 0V)

-2

µA

Input Leakage Address Current (All other pins not under test = 0V)

-10

µA

Output Leakage Current: I/Os are disabled; 0V V

OUT

CCQ

-5

µA

Output Levels: Full drive option (37, 39)
High Current (V

T = V

CCQ

- 0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

F, maximum V

)

-16.8

16.8

Output Levels: Reduced drive option (38, 39)
High Current (V

OUT

= V

CCQ

- 0.763V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.763V, maximum V

REF

, maximum V

)

OHR

-9

OLR

I/O Reference Voltage (6,44)

REF

0.49 x V

CCQ

0.51 x V

CCQ

I/O Termination Voltage (7, 44)

REF

- 0.04

REF

+ 0.04

AC INPUT OPERATING CONDITIONS

, V

CCQ

= +2.5V ± 0.2V; -55°C

+125°C

Parameter/Condition

Symbol

Min

Max

Units

Input High (Logic 1) Voltage

REF

+0.500

REF

-0.500

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Parameter/Condition

Symbol

333Mbs

250Mbs
266Mbs

200Mbs

Units

OPERATING CURRENT: One bank; Active-Precharge; t

= t

(MIN); t

= t

(MIN); DQ, DM, and DQS

inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22,
47)

CC0

650

575

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; t

= t

(MIN); t

= t

(MIN);

OUT

= 0mA; Address and control inputs changing once per clock cycle (22, 47)

CC1

800

725

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; t

= t

(MIN); CKE = LOW; (23, 32, 49)

CC2P

IDLE STANDBY CURRENT: CS = HIGH; All banks idle; t

= t

(MIN); CKE = HIGH; Address and other

control inputs changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM (50)

CC2F

225

200

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; t

= t

(MIN);

CKE = LOW (23, 32, 49)

CC3P

175

150

ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; t

= t

RAS

(MAX); t

= t

(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle (22)

CC3N

250

225

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control
inputs changing once per clock cycle; t

= t

(MIN); I

OUT

= 0mA (22, 47)

CC4R

825

725

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control
inputs changing once per clock cycle; t

= t

(MIN); DQ, DM, and DQS inputs changing twice per clock

cycle (22)

CC4W

975

755

675

AUTO REFRESH CURRENT t

REFC

= t

(MIN) (49)

CC5

1,450

1,400

REFC

= 7.8125µs (27, 49)

CC5A

SELF REFRESH CURRENT: CKE 0.2V Standard

(11)

CC6

OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, t

(MIN); t

(MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 48)

CC7

2,025

2,000

1,750

SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46)

, V

CCQ

= +2.5V ± 0.2V; -55°C

+125°C

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333Mbs

CL 2.5

266 Mbs CL 2.5

200 CL 2

250 Mbs CL2.5

200 Mbs CL2

200 Mbs CL2.5

150 Mbs CL2

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Units

Access window of DQs from CK/CK#

-0.70

+0.70

-0.75

+0.75

-0.8

+0.8

-0.8

+0.8

CK high-level width (30)

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width (30)

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5 (45, 51)

(2.5)

7.5

CL = 2 (45, 51)

(2)

DQ and DM input hold time relative to DQS (26, 31)

0.45

0.5

0.6

DQ and DM input setup time relative to DQS (26, 31) t

0.45

0.5

0.6

DQ and DM input pulse width (for each input) (31)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.6

+0.6

-0.75

+0.75

-0.8

+0.8 -0.8

+0.8 ns

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)

DQSQ

0.45

0.5

0.6

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period (34)

, t

Data-out high-impedance window from CK/CK# (18, 42)

+0.70

+0.75

+0.8

Data-out low-impedance window from CK/CK# (18, 42)

-0.70

-0.75

-0.8

Address and control input hold time (fast slew rate)

IHF

0.75

0.90

1.1

Address and control input setup time (fast slew rate)

ISF

0.75

0.90

1.1

Address and control input hold time (slow slew rate) (14)

IHS

0.8

1.1

Address and control input setup time (slow slew rate) (14)

ISS

0.8

1.1

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access (25, 26)

- t

QHS

-t

QHS

-t

QHS

-t

QHS

Data hold skew factor

QHS

0.55

0.75

ACTIVE to PRECHARGE command (35)

RAS

70,000

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period (49)

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble (43)

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble (43) t

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time (20, 21)

WPRES

DQS write postamble (19)

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (25)

- t

DQSQ

- t

DQSQ

- t

DQSQ

- t

DQSQ

REFRESH to REFRESH command interval (23) (Commercial & Industrial only)

REFC

70.3

µs

REFRESH to REFRESH command interval (23) (Military temperature only)*

REFC

35.15

µs

Average periodic refresh interval (23) (Commercial & Industrial only)

REFI

7.8

µs

Average periodic refresh interval (23) (Military temperature only)*

REFI

3.8

3.9

µs

Terminating voltage delay to VDD

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

* Self refresh available in commercial and industrial temperatures only.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

Notes 1-5, 14-17, 33

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NOTES:
1.

All voltages referenced to VSS.

2. Tests

for

AC timing, I

, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related specifi cations
and device operation are guaranteed for the full voltage range specifi ed.

Outputs measured with equivalent load:

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test

environment, but input timing is still referenced to V

REF

(or to the crossing point for

CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between V

(AC) and V

(AC).

5. The

AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard

(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

REF

is expected to equal V

CCQ/2

of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (noncommon mode) on V

REF

may

not exceed ±2 percent of the DC value. Thus, from V

CCQ/2

, V

REF

is allowed ±25mV

for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest V

REF

by-pass capacitor.

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

and must track variations

in the DC level of V

REF

is the magnitude of the difference between the input level on CK and the input

level on CK#.

The value of V

and V

are expected to equal V

CCQ/2

of the transmitting device

and must track variations in the DC level of the same.

10. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with minimum cycle time with the outputs open.

11. Enables on-chip refresh and address counters.
12. I

specifi cations are tested after the device is properly initialized, and is averaged

at the defi ned cycle rate.

13. This parameter is not tested but guaranteed by design. t

= 25°C, F= 1 MHz

14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew

rate is less than 0.5V/ns, timing must be derated: t

has an additional 50 ps per

each 100mV/ns reduction in slew rate from the 500mV/ns. t

has 0ps added, that

is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.

15. The

CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK# and CK# cross; the input reference level for signals other than CK/CK#
is V

REF

16. Inputs are not recognized as valid until V

REF

stabilizes. Once initialized, including

SELF REFRESH mode, V

REF

must be powered within specifi ed range. Exception:

during the period before V

REF

stabilizes, CKE

0.3 x V

CCQ

is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is V

18. t

and t

transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).

19. The intent of the Don't Care state after completion of the postamble is the DQS-

driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above V

DC(MIN) then it must not transition low (below

DC) prior to t

DQSH

(MIN).

20. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t

DQSS

22. MIN (t

or t

RFC

) for I

measurements is the smallest multiple of tCK that meets

the minimum absolute value for the respective parameter. t

RAS

(MAX) for I

measurements is the largest multiple of t

that meets the maximum absolute

value for t

RAS

23. The refresh period 64ms. (32ms for Military grade) This equates to an average

refresh rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this

maximum amount for any given device.

25. The valid data window is derived by achieving other specifi cations - t

CK/2

DQSQ

, and t

= t

- t

QHS

). The data valid window derates directly porportional

with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.

160

140

120

100

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

Reference

Point

30pF

Output
(V

OUT

)

FIG. A FULL DRIVE PULL-DOWN

CHARACTERISTICS

FIG. B FULL DRIVE PULL-UP

CHARACTERISTICS

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

CCQ -

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

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26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-

DQ15 of each chip.

27. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (t

RFC

[MIN]) else CKE is LOW (i.e.,

during standby).

28. To maintain a valid level, the transitioning edge of the input must:
a)

Sustain a constant slew rate from the current AC level through to the target AC
level, V

(AC) or V

(AC).

Reach at least the target AC level.

After the AC target level is reached, continue to maintain at least the target DC
level, V

(DC) or V

(DC).

29. The Input capacitance per pin group will not differ by more than this maximum

amount for any given device.

30. CK and CK# input slew rate must be

1V/ns (2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the

DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to t

and t

for each 100mV/ns reduction in slew rate. If slew rate exceeds

4V/ns, functionality is uncertain.

32. V

must not vary more than 4% if CKE is not active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to

vary by the same amount.

34. t

min is the lesser of t

minimum and t

minimum actually applied to the device

CK and CK# inputs, collectively during bank active.

35. READs and WRITEs with auto precharge are not allowed to be issued until

RAS

(MIN) can be satisfi ed prior to the internal precharge command being issued.

36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive. The average cannot be below the 2.5V minimum.

37. Normal Output Drive Curves:

The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.

The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.

The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.

The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.

The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.

The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves:

The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure C.

The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure C.

The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure D.

The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.

The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 V, and at the same voltage and temperature.

The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from a minimum V

level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus
will provide signifi cantly different voltage values.

40. V

overshoot: V

(MAX) = V

CCQ

+1.5V for a pulse width

3ns and the pulse width

can not be greater than 1/3 of the cycle rate. V

undershoot: V

(MIN) = -1.5V for a

pulse width

3ns and the pulse width cannot be greater than 1/3 of the cycle rate.

41. V

and V

CCQ

must track each other.

42. t

(MAX) will prevail over t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN) will

prevail over t

DQSCK

(MIN) + t

RPRE

(MAX) condition.

43. t

RPST

end point and t

RPRE

begin point are not referenced to a specifi c voltage level

but specify when the device output is no longer driving (t

RPST

), or begins driving

RPRE

44. During initialization, V

CCQ

, V

, and V

REF

must be equal to or less than V

+ 0.3V.

Alternatively, V

may be 1.35V maximum during power up, even if V

CCQ

are 0

volts, provided a minimum of 42 ohms of series resistance is used between the V

supply and the input pin.

45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.

As such, future die may not refl ect this option.

46. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or

LOW.

FIG. C REDUCED DRIVE PULL-DOWN

CHARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

FIG. D REDUCED DRIVE PULL-UP

CHARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

CCQ -

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

-10

-20

-30

-40

-50

-60

-70

-80

W3E32M72S-XSBX

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2006
Rev. 5

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

47. Random addressing changing: 50% of data changing at every transfer.
48. Random addressing changing: 100% of data changing at every transfer.
49. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t

RFC

has been satisfi ed.

50. I

CC2N

specifi es the DQ, DQS, and DQM to be driven to a valid high or low logic

level. I

CC2Q

is similar to I

CC2F

except I

CC2Q

specifi es the address and control inputs

to remain stable. Although I

CC2F

, I

CC2N

, and I

CC2Q

are similar, I

CC2F

is "worst case."

51. Whenever the operating frequency is altered, not including jitter, the DLL is

required to be reset followed by 200 clock cycles before any READ command.

52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20

MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.

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