1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
September 2004
Rev. 0
ADVANCED*
W3EG264M72EFSUxxxD4
White Electronic Designs
1GB 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA
FEATURES
Fast data transfer rate: PC-2100, PC-2700 and
PC3200
Clock speeds of 133 MHz, 166 MHz and 200MHz
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 3 and 4 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
Dual
Rank
V
CC
= V
CCQ
= +2.6V (200MHz)
V
CC
= V
CCQ
= +2.5V (133 and 166MHz)
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
PCB height option:
31.75 mm (1.25")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The W3EG264M72EFSU is a 2x64Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM components. The module consists of eighteen
64Mx8 DDR SDRAMs in FBGA packages mounted on a
200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
OPERATING FREQUENCIES
DDR400@CL=3
DDR333@CL=2.5
DDR266@CL=2
DDR266@CL=2.5
Clock Speed
200MHz
166MHz
133MHz
133MHz
CL-t
RCD
-t
RP
3-3-3
2.5-3-3
2-2-2
2.5-3-3
W3EG264M72EFSUxxxD4
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
PIN NAMES
Symbol
Description
WE#, CAS#, RAS# Command Input
CK0, CK0#
CK1, CK1#
CK2, CK2#
Clock Input
CKE0-CKE1
Clock Enable Input
S0#-S1#
Chip Select Input
BA0, BA1
Bank Address
A0-A12
Address input
SCL
Serial Clock
SA0-SA2
Presence Detect Address Input
SDA
Input/Output: Serial Presence-
Detect Data
DM0-DM8
Data Write Mask
DQS0-DQS8
Data Strobe
CB0-CB7
Input/Output: Check Bits
DQ0-DQ63
Input/Output: Data I/Os, Data bus
V
REF
Supply: SSTL_2 reference voltage
V
CC
Supply: Power Supply: +2.5V
0.2V
V
SS
Supply: Ground
V
CCSPD
Supply: Serial EEPROM Positive
Power Supply
NC
No Connect
DNU
Do Not Use
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
CK1#
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
CK1
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
CB0
121
S0#
171
DQ50
22
V
CC
72
CB4
122
S1#
172
DQ54
23
DQ9
73
CB1
123
NC
173
V
SS
24
DQ13
74
CB5
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
DQS8
127
DQ32
177
DQ56
28
V
SS
78
DM8
128
DQ36
178
DQ60
29
DQ10
79
CB2
129
DQ33
179
V
CC
30
DQ14
80
CB6
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
CB3
133
DQS4
183
DQS7
34
V
CC
84
CB7
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
DNU
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
CK2
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
CK2#
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
CKE1
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
NC
50
DQ22
100
A11
150
V
SS
200
V
SS
W3EG264M72EFSUxxxD4
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs U1-U9
CKE1: DDR SDRAMs U11-U19
WE#: DDR SDRAMs
CAS#
CKE0
CKE1
WE#
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U8
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
U0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
S0#
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
WP
SCL
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S1#
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DM8
DQS8
DM1
DQS1
DM7
DQS7
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM2
DQS2
DM6
DQS6
DM CS# DQS
DM CS# DQS
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQ
DM3
DQS3
DM5
DQS5
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
U17
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
V
DDSPD
V
DD
DDR SDRAMs
SPD/EEPROM
U1, U2, U5,
U13, U14, U19
CK0
CK0#
120
U3, U4, U9,
U11, U12, U15
CK1
CK1#
120
CK2
CK2#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM4
DQS4
DM CS# DQS
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
120
U6, U7, U8,
U16, U17, U18
NOTE: 1. All resistor values are 22 unless otherwise specified.
W3EG264M72EFSUxxxD4
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
DC ELECTRICAL CHARACTERISTICS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
V
CC
2.3
2.7
V
I/O Supply Voltage
V
CCQ
2.3
2.7
V
I/O Reference Voltage
V
REF
0.49 V
CCQ
0.51 V
CCQ
V
I/O Termination Voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
Input High (Logic 1) Voltage
V
IH
V
REF
+ 0.15
V
CC
+ 0.3
V
Input Low (Logic 0) Voltage
V
IL
-0.3
V
REF
- 0.15
V
High Current (V
OUT
= V
CCQ
- 0.373V, minimum V
REF
, minimum V
TT
)
V
OH
-16.8
--
mA
Low Current (V
OUT
= 0.373V, maximum V
REF
, maximum V
TT
)
V
OL
16.8
--
mA
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
Input/Output Capacitance: DQ, DQS,DM
C
I0
12
pF
Input Capacitance: Command and Address
C
I1
47
pF
Input Capacitance: CK, CK#,
C
I2
25
pF
Input Capacitance: CKE, S#
C
I3
25
pF
W3EG264M72EFSUxxxD4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
I
DD
SPECIFICATIONS AND CONDITIONS
0C T
A
+70C; V
CC
, V
CCQ
= +2.5V 0.2V
DDR400: V
CC
= V
CCQ
= +2.6V 0.2V
MAX
PARAMETER/CONDITION
SYM
DDR400
@CL=3
DDR333
@CL=2.5
DDR266
@CL=2
DDR266
@CL=2.5
UNITS
OPERATING CURRENT: One device bank; Active-Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
I
DD0
2475
2070
2070
1845
mA
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
I
DD1
2745
2340
2340
2115
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
I
DD2P
90
90
90
90
mA
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
CK
= t
CK
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VI
N
= V
REF
for DQ,
DQS, and DM
I
DD2F
990
810
810
720
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down
mode; t
CK
= t
CK
(MIN); CKE = LOW
I
DD3P
810
630
630
540
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
RC
=
t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
I
DD3N
1080
900
900
810
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
I
DD4R
2790
2385
2385
2115
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
I
DD4W
2790
2295
2295
2025
mA
AUTO REFRESH BURST CURRENT:
t
REFC
= t
RFC
(MIN)
I
DD5
4185
3510
3510
3330
mA
SELF REFRESH CURRENT: CKE 0.2V
I
DD6
90
90
90
90
mA
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, t
RC
= minimum t
RC
allowed; t
CK
= t
CK
(MIN); Address and control inputs change
only during Active READ, or WRITE commands
I
DD7
5130
4545
4545
3960
mA
W3EG264M72EFSUxxxD4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0C T
A
+70C; V
CC
= V
CCQ
= +2.5V 0.2V
AC CHARACTERISTICS
403
335
262
265
UNITS NOTES
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
t
AC
-0.65
+0.65
-0.70
+0.70
-0.75
+0.75
-0.75
0.75
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
CK low-level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
Clock cycle time
CL = 3
t
CK (3)
5
10
ns
39, 44
CL = 2.5
t
CK (2.5)
6
13
7.5
13
7.5
13
ns
39, 44
CL = 2
t
CK (2)
7.5
13
7.5
13
7.5/10
13
ns
39, 44
DQ and DM input hold time relative to DQS
t
DH
0.40
0.45
0.5
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
t
DS
0.40
0.45
0.5
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
t
DIPW
1.75
1.75
1.75
1.75
ns
27
Access window of DQS from CK/CK#
t
DQSCK
-0.55
+0.55
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
t
DQSH
0.35
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
t
DQSQ
0.4
0.4
0.5
0.5
ns
22, 23
Write command to fi rst DQS latching transition
t
DQSS
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.20
0.20
0.20
0.2
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.20
0.20
0.20
0.2
t
CK
Half clock period
t
HP
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
ns
30
Data-out high-impedance window from CK/CK#
t
HZ
+0.65
+0.70
+0.75
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
t
LZ
-0.65
+0.65
-0.70
-0.75
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
t
IHF
0.60
0.75
0.90
0.90
ns
12
Address and control input setup time (fast slew rate)
t
ISF
0.60
0.75
0.90
0.90
ns
12
Address and control input hold time (slow slew rate)
t
IHS
0.8
0.8
1
1
ns
12
W3EG264M72EFSUxxxD4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
0C < T
A
<+70C; V
CC
= V
CCQ
= +2.5V 0.2V
AC CHARACTERISTICS
403
335
262
265
UNITS NOTES
RAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Address and control input setup time (slow slew rate)
t
ISS
0.8
0.8
1
1
ns
12
Address and Control input pulse width (for each
input)
t
IPW
2.2
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
t
MRD
12
12
15
15
ns
DQ-DQS hold, DQS to fi rst DQ to go non-valid, per
access
t
QH
t
HP -
t
QHS
t
HP -
t
QHS
t
HP -
t
QHS
t
HP -
t
QHS
ns
22, 23
Data hold skew factor
t
QHS
0.50
0.50
0.75
0.75
ns
ACTIVE to PRECHARGE command
t
RAS
40
70,000
42
70,000
40
120,000
40
120,000
ns
30, 47
ACTIVE to READ with Auto precharge command
t
RAP
15
18
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
t
RC
55
60
60
65
ns
AUTO REFRESH command period
t
RFC
70
72
75
78
ns
42
ACTIVE to READ or WRITE delay
t
RCD
15
18
15
20
ns
PRECHARGE command period
t
RP
15
18
15
20
ns
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
37
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
37
ACTIVE bank a to ACTIVE bank b command
t
RRD
10
12
15
15
ns
DQS write preamble
t
WPRE
0.25
0.25
0.25
0.25
t
CK
DQS write preamble setup time
t
WPRES
0
0
0
0
ns
18, 19
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
17
Write recovery time
t
WR
15
15
15
15
ns
Internal WRITE to READ command delay
t
WTR
1
1
1
1
t
CK
Data valid output window
NA
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
ns
22
REFRESH to REFRESH command interval
t
REFC
70.3
70.3
70.3
70.3
s
21
Average periodic refresh interval
t
REFI
7.8
7.8
7.8
7.8
s
21
Terminating voltage delay to VDD
t
VTD
0
0
0
0
ns
Exit SELF REFRESH to non-READ command
t
XSNR
75
75
75
75
ns
Exit SELF REFRESH to READ command
t
XSRD
200
200
200
200
t
CK
W3EG264M72EFSUxxxD4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
Notes
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifi cations and device
operation are guaranteed for the full voltage range specifi ed.
3. Outputs measured with equivalent load:
Output
Output
(V
(V
OUT
OUT
)
Reference
Reference
Point
Point
50
50
V
TT
TT
30pF
30pF
4. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test
environment, but input timing is still referenced to V
REF
(or to the crossing point for
CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between V
IL
(AC) and V
IH
(AC).
5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC input
level, and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. V
REF
is expected to equal V
DDQ/2
of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (non-common mode) on V
REF
may not
exceed 2 percent of the DC value. Thus, from V
DDQ/2
, V
REF
is allowed 25mV for
DC error and an additional 25mV for AC noise. This measurement is to be taken at
the nearest V
REF
bypass capacitor.
7. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination
resistors, is expected to be set equal to V
REF
and must track variations in the DC
level of V
REF
.
8. I
DD
is dependent on output loading and cycle rates. Specifi ed values are obtained
with mini-mum cycle time at CL = 2 for -262, and -26A, CL = 2.5 for-335 and -265
with the outputs open.
9. Enables on-chip refresh and address counters.
10. I
DD
specifi cations are tested after the device is properly initialized, and is averaged
at the defi ned cycle rate.
11. This parameter is sampled. V
CC
= +2.5V 0.2V, V
CCQ
= +2.5V 0.2V, V
REF
= V
SS
, f
= 100 MHz, T
A
= 25C, V
OUT
(DC) = V
CCQ/2
, V
OUT
(peak to peak) = 0.2V. DM input is
grouped with I/O pins, refl ecting the fact that they are matched in loading.
12. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must
be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500mV/ns, while t
IH
is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For -335, slew rates must be 0.5 V/ns.
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
REF
.
14. Inputs are not recognized as valid until V
REF
stabilizes. Exception: during the period
before V
REF
stabilizes, CKE < 0.3 x V
CCQ
is recognized as LOW.
15. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is V
TT
.
16. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
17. The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above V
IH
DC (MIN) then it must not transition low (below V
IH
DC) prior to t
DQSH
(MIN).
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t
DQSS
.
20. MIN (t
RC
or t
RFC
) for I
DD
measurements is the smallest multiple of t
CK
that meets
the minimum absolute Value for the respective parameter. t
RAS
(MAX) for I
DD
measurements is the largest multiple of t
CK
that meets the maximum absolute value
for t
RAS
.
21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125s.
However, an AUTO REFRESH command must be asserted at least once every
70.3s; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
22. The valid data window is derived by achieving other specifi cations: t
HP
(t
CK/2
), t
DQSQ
,
and t
QH
(t
QH
= t
HP
- t
QHS
). The data valid window derates directly porportional with
the clock duty cycle and a practical data valid window can be derived. The clock
is allowed a maximum duty cycle variation of 45/55, beyon which functionality is
uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty
cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (t
RFC
[MIN]) else CKE is LOW (i.e., during
standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, V
IL
(AC) or V
IH
(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, V
IL
(DC) or V
IH
(DC).
26. JEDEC specifi es CK and CK# input slew rate must be 1V/ns (2V/ns differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.
If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps
must be added to t
DS
and t
DH
for each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns.
28. V
CC
must not vary more than 4 percent if CKE is not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary
by the same amount. t
HP
min is the lesser of t
CL
minimum and t
CH
minimum actually
applied to the device CK and CK# inputs, collectively during bank active.
30. READs and WRITEs with auto precharge are not allowed to be issued until
t
RAS
(MIN) can be satisfi ed prior to the internal precharge command being issued.
31. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9V, which-ever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either - 300mV or 2.2V, whichever is more positive.
W3EG264M72EFSUxxxD4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
32. Normal Output Drive Curves:
a. The full variation in driver pull-down current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure 8, Pull-Down Characteristics.
b. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, Pull-Down Characteristics.
c. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure 9, Pull-Up Characteristics.
d. The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 9, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between 0.71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0V, and at the same voltage and temperature.
f. The full variation in the ratio of the nominal pull-up to pull-down current should be
unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
33. The voltage levels used are derived from a mini-mum V
CC
level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signifi cantly different voltage values.
34. V
IH
overshoot: V
IH
(MAX) = V
CCQ
+ 1.5V for a pulse width < 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -1.5V for a
pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
35. V
CC
and V
CCQ
must track each other.
36. t
HZ
(MAX) will prevail over t
DQSCK
(MAX) + t
RPST
(MAX) condition. t
LZ
(MIN) will
prevail over t
DQSCK
(MIN) + t
RPRE
(MAX) condition.
37. t
RPST
end point and t
RPRE
begin point are not referenced to a specifi c voltage level
but specify when the device output is no longer driving (t
RPST
), or begins driving
(t
RPRE
).
38. During Initialization, V
CCQ
, V
TT
, and V
REF
must be equal to or less than V
CC
+ 0.3V.
Alternatively, V
TT
may be 1.35V maximum during power up, even if V
CC
/V
CCQ
are
0.0V, provided a minimum of 42 0 of series resistance is used between the V
TT
supply and the input pin.
39. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not refl ect this option.
40. Random addressing changing and 50 percent of data changing at every transfer.
41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t
REF
later.
43. I
DD2N
specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.
I
DD2Q
is similar to I
DD2F
except I
DD2Q
specifi es the address and control inputs to
remain stable. Although I
DD2F
, I
DD2N
, and I
DD2Q
are similar, I
DD2F
is "worst case."
44. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles.
45. Leakage number refl ects the worst case leakage possible through the module pin,
not what each memory device contributes.
46. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or
LOW.
47. The -335 speed grade will operate with t
RAS
(MIN) = 40ns and t
RAS
(MAX) =
120,000ns at any slower frequency.
W3EG264M72EFSUxxxD4
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
200-PIN DDR SO-DIMM DIMENSIONS
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
W3EG264M72EFSU403D4
200MHz/400Mbps
3
3
3
31.75 (1.25") MAX
W3EG264M72EFSU335D4
166MHz/333Mbps
2.5
3
3
31.75 (1.25") MAX
W3EG264M72EFSU262D4
133MHz/266Mbps
2
2
2
31.75 (1.25") MAX
W3EG264M72EFSU265D4
133MHz/266Mbps
2.5
3
3
31.75 (1.25") MAX
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.81 (0.150 )
MAX
1.10 (0.043)
PIN 1
67.56 (2.66)
20.00 (0.787)
TYP
1.80 (0.071)
(2X)
0.61 (0.024)
TYP
0.46 (0.018)
TYP
2.00 (0.079) R
(2X)
PIN 199
PIN 200
PIN 2
FRONT VIEW
2.00 (0.079)
6.00 (0.236)
63.60 (2.504)
2.44 (0.096)
0.99 (0.039)
TYP
31.75
(1.25)
TYP
BACK VIEW
W3EG264M72EFSUxxxD4
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
PART NUMBERING GUIDE
W 3 E G 264M 72 E F S U xxx D4
WEDC
MEMORY
DDR
GOLD
DEPTH (Dual Rank)
BUS WIDTH
x8
FBGA
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 200 PIN
W3EG264M72EFSUxxxD4
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
Document Title
1GB 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
9-04
Advanced
PDF 
ZIP