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PRELIMINARY*

May 2005
Rev. 6

W3EG6432S-D3

-JD3

FEATURES

Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400

· JEDEC design specifi cations

Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:

· V

= V

CCQ

= +2.5V ±0.2V (100, 133 and

166MHz)

· V

= V

CCQ

= +2.6V ±0.1V (200MHz)

JEDEC standard 184 pin DIMM package

· JD3 PCB height: 30.48 (1.20") max

NOTE: Consult factory for availability of:

Lead-free

products

· Vendor source control option
· Industrial temperature option

DESCRIPTION

The W3EG6432S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.

256MB 32Mx64 DDR SDRAM UNBUFFERED

OPERATING FREQUENCIES

DDR400 @CL=3

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

200MHz

166MHz

133MHz

100MHz

CL-t

RCD

-t

3-3-3

2.5-3-3

2-2-2

2-3-3

2.5-3-3

2-2-2

White Electronic Designs

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

REF

139

DQ0

DQ4

140

DQ5

141

A10

DQ1

CCQ

142

DQS0

DQM0

143

CCQ

DQ2

BA1

DQ6

144

DQ32

DQ7

145

DQ3

CCQ

100

146

DQ36

DQ33

101

147

DQ37

DQS4

102

148

DQ34

103

149

DQM4

DQ8

104

CCQ

150

DQ38

DQ9

BA0

105

DQ12

151

DQ39

DQS1

DQ35

106

DQ13

152

CCQ

DQ40

107

DQM1

153

DQ44

CK1

CCQ

108

154

RAS#

CK1#

WE#

109

DQ14

155

DQ45

DQ41

110

DQ15

156

CCQ

DQ10

CAS#

111

157

CS0#

DQ11

112

CCQ

158

CKE0

DQS5

113

159

DQM5

CCQ

DQ42

114

DQ20

160

DQ16

DQ43

115

A12

161

DQ46

DQ17

116

162

DQ47

DQS2

117

DQ21

163

DQ48

118

A11

164

CCQ

DQ49

119

DQM2

165

DQ52

DQ18

120

166

DQ53

CK2#

121

DQ22

167

CCQ

CK2

122

168

DQ19

CCQ

123

DQ23

169

DQM6

DQS6

124

170

DQ54

DQ24

DQ50

125

171

DQ55

DQ51

126

DQ28

172

CCQ

DQ25

127

DQ29

173

DQS3

CCID

128

CCQ

174

DQ60

DQ56

129

DQM3

175

DQ61

DQ57

130

176

DQ26

131

DQ30

177

DQM7

DQ27

DQS7

132

178

DQ62

DQ58

133

DQ31

179

DQ63

DQ59

134

180

CCQ

135

181

SA0

136

CCQ

182

SA1

SDA

137

CK0

183

SA2

SCL

138

CK0#

184

CCSPD

PIN CONFIGURATION

A0-A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

DQS0-DQS7

Data Strobe Input/Output

CK0, CK1, CK2

Clock Input

CK0#, CK1#, CK2#

Clock Input

CKE0

Clock Enable input

CS0#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQM0-DQM7

Data-in-mask

Power Supply

CCQ

Power Supply for DQS

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

PIN NAMES

White Electronic Designs

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May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 to 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 to 3.6

Storage Temperature

STG

-55 to +150

°C

Power Dissipation

Short Circuit Current

Note:

Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C

70°C, V

= V

CCQ

= 2.5V ± 0.2V, V

= V

CCQ

= 2.6V ± 0.1V (200MHz)

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

1.15

1.35

Termination Voltage

1.15

1.35

Input High Voltage

REF

+ 0.15

CCQ

+ 0.3

Input Low Voltage

-0.3

REF

-0.15

Output High Voltage

+ 0.76

Output Low Voltage

-0.76

CAPACITANCE

= 25°C, f = 1MHz, V

= V

CCQ

= 2.5V ± 0.2V, V

= V

CCQ

= 2.6V ± 0.1V (200MHz)

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

Input Capacitance (RAS#,CAS#,WE#)

IN2

Input Capacitance (CKE0, CKE1)

IN3

Input Capacitance (CK0#,CK0)

IN4

Input Capacitance (CS0#, CS1#)

IN5

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

White Electronic Designs

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May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

= V

CCQ

= 2.5V ± 0.2V, V

= V

CCQ

= 2.6V ± 0.1V (200MHz)V

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR400@

CL=3

Max

DDR333@

CL=2.5-3-3

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

DDR200@

CL=2

Max

Units

Operating Current

DD0

One device bank; Active - Precharge;
t

(MIN); t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.

1080

1000

Operating Current

DD1

One device bank; Active-Read-
Precharge Burst = 2; t

(MIN);

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per
clock cycle.

1360

1200

Precharge Power-
Down Standby
Current

DD2P

All device banks idle; Power-down
mode; t

(MIN); CKE=(low)

rnA

Idle Standby Current

DD2F

CS# = High; All device banks idle;
t

(MIN); CKE = high; Address

and other control inputs changing once
per clock cycle. V

= V

REF

for DQ,

DQS and DM.

480

400

360

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down
mode; t

(MIN); CKE=(low)

320

240

200

Active Standby
Current

DD3N

CS# = High; CKE = High; One device
bank; Active-Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.

560

480

400

Operating Current

DD4R

Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; T

= T

(MIN); l

OUT

= 0mA.

1600

1400

1200

Operating Current

DD4W

Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t

(MIN); DQ,DM and DQS

inputs changing once per clock cycle.

1560

1400

1200

rnA

Auto Refresh Current

DD5

= t

(MIN)

2080

2040

1880

Self Refresh Current

DD6

CKE

0.2V

Operating Current

DD7A

Four bank interleaving Reads (BL=4)
with auto precharge with t

(MIN);

(MIN); Address and control

inputs change only during Active Read
or Write commands.

3760

3280

2800

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May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

DD1

: OPERATING CURRENT : ONE BANK

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

CK=

10ns, CL2,

BL=4, t

RCD=

2*t

, t

RAS=

5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

CK=

7.5ns,

CL=2.5, BL=4, t

RCD=

3*t

, t

RC=

9*t

, t

RAS=

5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL=2,

BL=4, t

RCD

=3*t

, t

=9*t

, t

RAS

=5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR333 (166MHz, CL=2.5) : t

=6ns, BL=4,

RCD

=10*t

, t

RAS

=7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR400 (200MHz, CL=3) : t

=5ns, BL=4,

RCD

=15*t

, t

RAS

=7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: OPERATING CURRENT : FOUR BANKS

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

=10ns, CL2,

BL=4, t

RRD

=2*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL=2.5) : t

=7.5ns,

CL=2.5, BL=4, t

RRD

=3*t

, t

RCD

=3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL2=2,

BL=4, t

RRD

=2*t

, t

RCD

=2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR333 (166MHz, CL=2.5) : t

=6ns,

BL=4, t

RRD

=3*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR400 (200MHz, CL=3) : t

=5ns,

BL=4, t

RRD

=10*t

, t

RCD

=15*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3

R (0-3) = Read Bank 0-3

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May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

AC CHARACTERISTICS

403

335

262

263/265

202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX UNITS NOTES

Access window of DQs from CK/CK#

-0.7

+0.7

-0.7

+0.7

-0.75 +0.75 -0.75 +0.75 -0.75 +0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 3

tCK (3)

7.5

40, 45

CL = 2.5

CK (2.5)

7.5

40, 45

CL = 2

CK (2)

7.5

7.5/10

40, 45

DQ and DM input hold time relative to DQS

0.4

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.4

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per
access

DQSQ

0.40

0.45

0.5

22, 23

Write command to fi rst DQS latching transition

DQSS

0.72

1.28

0.75

1.25

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 36

Data-out low-impedance window from CK/CK#

-0.70

-0.75

16, 36

Address and control input hold time (fast slew rate)

IHF

0.6

0.75

0.90

.90

Address and control input setup time (fast slew rate)

ISF

0.6

0.75

0.90

.90

Address and control input hold time (slow slew rate)

IHS

0.6

0.80

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May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

AC CHARACTERISTICS

403

335

262

263/265

202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX UNITS NOTES

Address and control input setup time (slow slew rate)

ISS

0.6

0.80

Address and Control input pulse width (for each
input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per
access

QHS

22, 23

Data hold skew factor

QHS

0.50

0.55

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

31, 48

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command
period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

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Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

Notes
1.

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC characteristics may

be conducted at nominal reference/supply voltage levels, but the related
specifi cations and device operation are guaranteed for the full voltage range
specifi ed.

Outputs measured with equivalent load:

Output

Output
(V

OUT

)

Reference

Point

30pF

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test

environment, but input timing is still referenced to V

REF

(or to the crossing point

for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC
input levels under normal use conditions. The mini-mum slew rate for the input
signals used to test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

CCQ

/2 of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (non-common mode) on V

REF

may not exceed ±2 percent of the DC value. Thus, from V

CCQ

/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for AC noise. This measurement is
to be taken at the nearest V

REF

bypass capacitor.

7. V

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with mini-mum cycle time at CL = 2 for 262, and 262, CL = 2.5 for 335 and 265,
CL = for 403 with the outputs open.

Enables on-chip refresh and address counters.

10. I

specifi cations are tested after the device is properly initialized, and is

averaged at the defi ned cycle rate.

11.

This parameter is sampled. V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V, V

REF

= V

f = 100 MHz, TA = 25°C, V

OUT

(DC) = V

CCQ

/2, V

OUT

(peak to peak) = 0.2V. DM

input is grouped with I/O pins, refl ecting the fact that they are matched in loading.

12.

For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate
is less than 0.5 V/ns, timing must be derated: t

has an additional 50ps per each

100mV/ns reduction in slew rate from 500mV/ns, while t

is unaffected. If slew

rate exceeds 4.5V/ns, functionality is uncertain.

13.

The CK/CK# input reference level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference level for signals other than
CK/CK# is V

REF

14.

Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the

period before V

REF

stabilizes, CKE < 0.3 x V

CCQ

is recognized as LOW.

15.

The output timing reference level, as measured at the timing reference point
indicated in Note 3, is V

16. t

and t

transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).

17.

The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above V

IHDC

(MIN)] then it must not transition low (below

IHDC

) prior to t

DQSH

(MIN).

18.

This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.

19.

It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t

DQSS

20. MIN

or t

RFC

) for I

measurements is the smallest multiple of t

that meets

the minimum absolute value for the respective parameter. t

RAS

(MAX) for I

measurements is the largest multiple of t

that meets the maximum absolute

value for t

RAS

21.

The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.

22.

The valid data window is derived by achieving other specifi cations: t

CK/2

DQSQ

, and t

= t

- t

QHS

). The data valid window derates directly

porportional with the clock duty cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond
which functionality is uncertain.

23.

Each byte lane has a corresponding DQS: x8 = DQS with DQ0-DQ7.

24.

This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (t

RFC

[MIN]) else CKE is LOW (i.e.,

during standby).

25.

To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through to the target

AC level, V

(AC) or V

(AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to maintain at least the target DC

level, V

(DC) or V

(DC).

26.

JEDEC specifi es CK and CK# input slew rate must be 1V/ns (2V/ns if
measured differentially).

27.

DQ and DM input slew rates must not deviate from DQS by more than 10
percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to t

and t

for each 100mv/ns reduction in slew

rate. If slew rate exceeds 4V/ns, functionality is uncertain.

28. V

must not vary more than 4 percent if CKE is not active while any bank is

active.

29.

The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to
vary by the same amount.

30. t

min is the lesser of t

minimum and t

minimum actually applied to the

device CK and CK# inputs, collectively during bank active.

31.

READs and WRITEs with auto precharge are not allowed to be issued until t

RAS

(MIN) can be satisfi ed prior to the internal precharge command being issued.

32.

Any positive glitch in the nominal voltage must be less than 1/3 of the clock and
not more than +400mV or 2.9V, whichever is less. Any negative glitch must be
less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever
is more positive. However, the DC average cannot be below 2.3V minimum.

White Electronic Designs

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

33.

The voltage levels used are derived from a mini-mum V

level and the

referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide signifi cantly different voltage values.

34. V

overshoot: V

(MAX) = V

CCQ

+ 1.5V for a pulse width 3ns and the pulse

width can not be greater than 1/3 of the cycle rate. V

undershoot: V

(MIN) =

-1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of
the cycle rate.

35. V

and V

CCQ

must track each other.

36. t

(MAX) takes precedence over t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN)

will prevail over t

DQSCK

(MIN) + t

RPRE

(MAX) condition.

37. t

RPST

end point and t

RPRE

begin point are not referenced to a specifi c voltage level

but specify when the device output is no longer driving (t

RPST

), or begins driving

RPRE

38.

During initialization, V

CCQ

, V

, and V

REF

must be equal to or less than V

0.3V. Alternatively, V

may be 1.35V maximum during power up, even if V

CCQ

are 0V, provided a minimum of 42 of series resistance is used between

the V

supply and the input pin.

39.

For 403, 335, 262, 263 and 265 speed grades, I

DD3N

is specifi ed to be 35mA per

DDR SDRAM at 100 MHz.

40.

The current part operates below the slowest JEDEC operating frequency of
83 MHz. As such, future die may not refl ect this option.

41.

Random addressing changing and 50 percent of data changing at every transfer.

42.

Random addressing changing and 100 percent of data changing at every
transfer.

43.

CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t

REF

has been satisfi ed.

44. I

DD2N

specifi es the DQ, DQS, and DM to be driven to a valid high or low logic

level. I

DD2Q

is similar to I

DD2F

except I

DD2Q

specifi es the address and control inputs

to remain stable. Although I

DD2F

, I

DD2N

, and I

DD2Q

are similar, I

DD2F

is "worst case."

45.

Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset. This is followed by 200 clock cycles.

46.

Leakage number refl ects the worst case leakage possible through the module
pin, not what each memory device contributes.

47.

When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH
or logic LOW.

48.

The 403 speed grade will operate with t

RAS

(MIN) = 40ns and t

RAS

(MAX) =

120,000ns at any slower frequency.

White Electronic Designs

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

133.48

(5.255" MAX.)

3.99

(0.157 (2x))

17.78

(0.700)

10.01

(0.394)

6.35

(0.250)

64.77

(2.550)

1.78

(0.070)

49.53

(1.950)

3.00

(0.118)

(4x)

30.48

(1.20)

MAX

2.31

(0.091)

(2x)

1.27

(0.050 TYP.)

6.35

(0.250)

128.95

(5.077")

131.34

(5.171")

2.54

(0.100 MAX)

3.99

(0.157)

(MIN)

1.27 ± 0.10

(0.050 ± 0.004)

PACKAGE DIMENSIONS FOR JD3

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR JD3

Part Number

Speed

CAS Latency

RCD

Height*

Temperature

W3EG6432S403JD3

200MHz/400Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S335JD3

166MHz/333Mb/s

2.5

30.48 (1.20")

0°C to 70°C

W3EG6432S262JD3

133MHz/266Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S263JD3

133MHz/266Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S265JD3

133MHz/266Mb/s

2.5

30.48 (1.20")

0°C to 70°C

W3EG6432S202JD3

100MHz/200Mb/s

30.48 (1.20")

0°C to 70°C

NOTE:
1

* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)

* Product specifi c part numbers are available for source control if needed, please consult factory for the correct part number if a specifi c component vendor is preferred.

* Consult factory for availability for industrial temperature (-40°C to 85°C) options

White Electronic Designs

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

May 2005
Rev. 6

PRELIMINARY

W3EG6432S-D3

-JD3

133.48

(5.255" MAX.)

3.99

(0.157 (2x))

17.78

(0.700)

10.01

(0.394)

6.35

(0.250)

64.77

(2.550)

1.78

(0.070)

49.53

(1.950)

3.00

(0.118)

(4x)

30.48

(1.20)

MAX

2.31

(0.091)

(2x)

1.27

(0.050 TYP.)

6.35

(0.250)

128.95

(5.077")

131.34

(5.171")

2.54

(0.100 MAX)

3.99

(0.157)

(MIN)

1.27 ± 0.10

(0.050 ± 0.004)

PACKAGE DIMENSIONS FOR D3

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D3

Part Number

Speed

CAS Latency

RCD

Height*

Temperature

W3EG6432S403D3

200MHz/400Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S335D3

166MHz/333Mb/s

2.5

30.48 (1.20")

0°C to 70°C

W3EG6432S262D3

133MHz/266Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S263D3

133MHz/266Mb/s

30.48 (1.20")

0°C to 70°C

W3EG6432S265D3

133MHz/266Mb/s

2.5

30.48 (1.20")

0°C to 70°C

W3EG6432S202D3

100MHz/200Mb/s

30.48 (1.20")

0°C to 70°C

NOTE:
1

* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)

* Product specifi c part numbers are available for source control if needed, please consult factory for the correct part number if a specifi c component vendor is preferred.

* Consult factory for availability for industrial temperature (-40°C to 85°C) options

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