1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2004
Rev. 6
PRELIMINARY*
W3EG6432S-D4
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
DDR266 @CL=2.5
DDR266 @CL=2
DDR200 @CL=2
Clock Speed
166MHz
133MHz
133MHz
133MHz
100MHz
CL-t
RCD
-t
RP
2.5-3-3
2-2-2
2.5-3-3
2-3-3
2-2-2
256MB 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
DDR200, DDR266 and DDR333
JEDEC
design
specifi
cations
Double-data-rate
architecture
Industrial temperature
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V 0.20V
Industrial temperature options
Standard 200 pin SO-DIMM package
Package height option:
D4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
Lead-free
products
Vendor source control option
Industrial temperature option
DESCRIPTION
The W3EG6432S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 200
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
CK1#
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
CK1
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DQM0
62
DQM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10/AP
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DQM6
21
V
CC
71
NC
121
CS0#
171
DQ50
22
V
CC
72
NC
122
NC
172
DQ54
23
DQ9
73
NC
123
NC
173
V
SS
24
DQ13
74
NC
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DQM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
NC
127
DQ32
177
DQ56
28
V
SS
78
NC
128
DQ36
178
DQ60
29
DQ10
79
NC
129
DQ33
179
V
CC
30
DQ14
80
NC
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
NC
133
DQS4
183
DQS7
34
V
CC
84
NC
134
DQM4
184
DQM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
NC
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
NC
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
NC
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
NC
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DQM2
98
NC
148
DQM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
V
CCID
50
DQ22
100
A11
150
V
SS
200
NC
PIN NAMES
A0-A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
DQS0-DQS7
Data Strobe Input/Output
CK0, CK1
Clock Input
CK0#, CK1#
Clock Input
CKE0
Clock Enable input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-DQM7
Data-In Mask
V
CC
Power Supply
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Indentifi cation Flag
NC
No Connect
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs
WE#: DDR SDRAMs
CAS#
CKE0
WE#
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM0
CS0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WP
SCL
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DQM4
DQS4
DQM1
DQS1
DQM5
DQS5
DQM2
DQS2
DQM6
DQS6
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQM3
DQS3
DQM7
DQS7
V
CC
SPD
V
CC
DDR SDRAMs
SPD
DDR SDRAM X 4
CK0
CK0#
120
DDR SDRAM X 4
CK1
CK1#
120
NOTE: All resistor values are 22 ohms unless otherwise specifi ed
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
8
W
Short Circuit Current
I
OS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= 2.5V 0.2V
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 2.5 0.2V, V
REF
=1.4V 200mV
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
2.3
2.7
V
Supply Voltage
V
CCQ
2.3
2.7
V
Reference Voltage
V
REF
V
CCQ/2
- 50mV
V
CCQ/2
+ 50mV
V
Termination Voltage
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
Input High Voltage
V
IH
V
REF
+ 0.15
V
CCQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
V
REF
- 0.15
V
Output High Voltage
V
OH
V
TT
+ 0.76
--
V
Output Low Voltage
V
OL
--
V
TT
- 0.76
V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
29
pF
Input Capacitance (RAS#, CAS#, WE#)
C
IN2
29
pF
Input Capacitance (CKE0)
C
IN3
29
pF
Input Capacitance (CK0,CK0#)
C
IN4
29
pF
Input Capacitance (CS0#)
C
IN5
29
pF
Input Capacitance (DQM0-DQM7)
C
IN6
8
pF
Input Capacitance (BA0-BA1)
C
IN7
29
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
C
OUT
8
pF
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0C
T
A
70C, V
CC
= 2.5V 0.2V
DDR SDRAM Component Values Only
Parameter
Symbol Conditions
DDR333
@CL=2.5
Max
DDR266
@CL=2
Max
DDR266
@CL=2.5
Max
DDR266
@CL=2
Max
DDR200
@CL=2
Max
Units
Operating Current
I
DD0
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
1000
1000
1000
1000
1000
mA
Operating Current
I
DD1
One device bank; Active-Read-Precharge;
Burst = 2; t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
1360
1280
1280
1280
1280
mA
Precharge Power-
Down Standby
Current
I
DD2P
All device banks idle; Power- down mode;
t
CK
=t
CK
(MIN); CKE=(low)
32
32
32
32
32
mA
Idle Standby
Current
I
DD2F
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
400
360
360
360
360
mA
Active Power-Down
Standby Current
I
DD3P
One device bank active; Power-down mode;
t
CK
(MIN); CKE=(low)
240
200
200
200
200
mA
Active Standby
Current
I
DD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX);
t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
480
400
400
400
400
mA
Operating Current
I
DD4R
Burst = 2; Reads; Continous burst; One
device bank active;Address and control inputs
changing once per clock cycle; t
CK
=t
CK
(MIN);
Iout = 0mA.
1400
1200
1200
1200
1200
mA
Operating Current
I
DD4W
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
changing once per clock cycle; t
CK
=t
CK
(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
1400
1200
1200
1200
1200
mA
Auto Refresh
Current
I
DD5
t
RC
=t
RC
(MIN)
2040
1880
1880
1880
1880
mA
Self Refresh
Current
I
DD6
CKE
0.2V
32
32
32
32
32
mA
Operating Current
I
DD7A
Four bank interleaving Reads (BL=4) with auto
precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN);
Address and control inputs change only
during Active Read or Write commands.
3280
2800
2800
2800
2800
mA
PDF 
ZIP