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Электронный компонент: W3EG6464S262BD4

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W3EG6464S-AD4
-BD4
PRELIMINARY*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL
Double-data-rate
architecture
Speeds of 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable
Burst
Length
(2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power
supply:
V
CC
: 2.5V 0.2V
JEDEC standard 200 pin SO-DIMM package
Package height options:
AD4: 35.5 mm (1.38"),
BD4: 31.75 (1.25")
The W3EG6464S is a 64Mx64 Double Data Rate
SDRAM mem o ry module based on 512Mb DDR SDRAM
component. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 200
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
DESCRIPTION
FEATURES
OPERATING FREQUENCIES
DDR333@CL=2.5
DDR266@CL=2
DDR266@CL=2.5
DDR200@CL=2
Clock Speed
166MHz
133MHz
133MHz
100MHz
CL-t
RCD
-t
RP
2.5-3-3
2-2-2
2.5-3-3
2-2-2
W3EG6464S-AD4
-BD4
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
NC
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
NC
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10/AP
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
NC
121
CS0
171
DQ50
22
V
CC
72
NC
122
NC
172
DQ54
23
DQ9
73
NC
123
NC
173
V
SS
24
DQ13
74
NC
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
DQS8
127
DQ32
177
DQ56
28
V
SS
78
DM8
128
DQ36
178
DQ60
29
DQ10
79
NC
129
DQ33
179
V
CC
30
DQ14
80
NC
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
NC
133
DQS4
183
DQS7
34
V
CC
84
NC
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
NC
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
NC
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
NC
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
NC
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
V
CCID
50
DQ22
100
A11
150
V
SS
200
NC
PIN CONFIGURATION
A0-A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
DQS0-DQS8
Data Strobe Input/Output
CK0
Clock Input
CK0#
Clock Input
CKE0
Clock Enable input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-DQM8
Data-In Mask
V
CC
Power Supply (2.5V)
V
CCQ
Power Supply for DQS (2.5V)
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
(2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Indentifi cation Flag
NC
No Connect
PIN NAMES
W3EG6464S-AD4
-BD4
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CK0
CK0
WE#, RAS#, CAS#
WE#, RAS#, CAS#
S0#
S0#
CKE0
CKE0
BA0, BA1, A0-A13
BA0, BA1, A0-A13
DQ0-7
DQ0-7
DQ0-7
DQ0-7
DQ0-7
DQ0-7
DQ32-39
DQ32-39
LDQM
LDQM
DQMB0
DQMB0
U1
U1
PLL
PLL
U3
U3
LDQM
LDQM
DQMB4
DQMB4
DQ0-7
DQ0-7
DQ8-15
DQ8-15
DQ0-7
DQ0-7
DQ40-47
DQ40-47
LDQM
LDQM
DQMB1
DQMB1
U2
U2
U4
U4
LDQM
LDQM
DQMB5
DQMB5
DQ0-7
DQ0-7
DQ16-23
DQ16-23
DQ0-7
DQ0-7
DQ48-55
DQ48-55
LDQM
LDQM
DQMB2
DQMB2
U5
U5
U7
U7
LDQM
LDQM
DQMB6
DQMB6
DQ0-7
DQ0-7
DQ24-31
DQ24-31
DQ0-7
DQ0-7
DQ56-63
DQ56-63
LDQM
LDQM
DQMB3
DQMB3
U6
U6
U8
U8
LDQM
LDQM
DQMB7
DQMB7
SA0
SA0
A0
A0
SCL
SCL
WP
WP
SDA
SDA
SA2
SA2
SA1
SA1
A2
A2
A1
A1
SERIAL
SERIAL PD
PD
CK0#
CK0#
DDR
DDR SDRAM
SDRAM U1
U1
DDR
DDR SDRAM
SDRAM U2
U2
DDR
DDR SDRAM
SDRAM U3
U3
DDR
DDR SDRAM
SDRAM U4
U4
DDR
DDR SDRAM
SDRAM U5
U5
DDR
DDR SDRAM
SDRAM U6
U6
DDR
DDR SDRAM
SDRAM U7
U7
DDR
DDR SDRAM
SDRAM U8
U8
120
120 W
W3EG6464S-AD4
-BD4
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
8
W
Short Circuit Current
I
OS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= 2.5V 0.2V
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 3.3V, V
REF
=1.4V 200mV
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
2.3
2.7
V
Supply Voltage
V
CCQ
2.3
2.7
V
Reference Voltage
V
REF
V
CCQ/2
- 50mV
V
CCQ/2
+ 50mV
V
Termination Voltage
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
Input High Voltage
V
IH
V
REF
+ 0.15
V
CCQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
V
REF
- 0.15
V
Output High Voltage
V
OH
V
TT
+ 0.76
--
V
Output Low Voltage
V
OL
--
V
TT
- 0.76
V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
26
pF
Input Capacitance (RAS#, CAS#, WE#)
C
IN2
26
pF
Input Capacitance (CKE0)
C
IN3
26
pF
Input Capacitance (CK0,CK0#)
C
IN4
5.5
pF
Input Capacitance (CS0#)
C
IN5
26
pF
Input Capacitance (DQM0-DQM8)
C
IN6
8
pF
Input Capacitance (BA0-BA1)
C
IN7
26
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
C
OUT
8
pF
W3EG6464S-AD4
-BD4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0C
T
A
70C, V
CCQ
= 2.5V 0.2V, V
CC
= 2.5V 0.2V
Parameter
Symbol Conditions
DDR333
@CL=2.5
Max
DDR266
@CL=2
Max
DDR266
@CL=2.5
Max
DDR200
@CL=2
Max
Units
Operating Current
I
DD0
One device bank; Active - Precharge; t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs changing once per
clock cycle; Address and control inputs changing once every
two cycles.
TBD
1595
1595
1595
mA
Operating Current
I
DD1
One device bank; Active-Read-Precharge; Burst = 2;
t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
TBD
1795
1795
1795
mA
Precharge Power-Down
Standby Current
I
DD2P
All device banks idle; Power- down mode; t
CK
=t
CK
(MIN);
CKE=(low)
TBD
48
48
48
mA
Idle Standby Current
I
DD2F
CS# = High; All device banks idle; t
CK
=t
CK
(MIN); CKE = high;
Address and other control inputs changing once per clock
cycle. Vin = Vref for DQ, DQS and DM.
TBD
675
675
675
mA
Active Power-Down
Standby Current
I
DD3P
One device bank active; Power-down mode; t
CK
(MIN);
CKE=(low)
TBD
400
400
400
mA
Active Standby Current
I
DD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
TBD
1035
1035
1035
mA
Operating Current
I
DD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address and control inputs changing once per clock
cycle; t
CK
=t
CK
(MIN); Iout = 0mA.
TBD
2035
2035
2035
mA
Operating Current
I
DD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
TBD
2275
2275
2275
mA
Auto Refresh Current
I
DD5
t
RC
=t
RC
(MIN)
TBD
2755
2755
2755
mA
Self Refresh Current
I
DD6
CKE
0.2V
TBD
315
315
315
mA
Operating Current
I
DD7A
Four bank interleaving Reads (BL=4) with auto precharge
with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and control inputs
change only during Active Read or Write commands.
TBD
4115
4115
4115
mA
* For DDR333 consult factory
W3EG6464S-AD4
-BD4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical
Case
:
V
CC
=2.5V, T=25C
2. Worst
Case
:
V
CC
=2.7V, T=10C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing
Patterns
:
DDR200 (100 MHz, CL=2) : t
CK=
10ns, CL2,
BL=4, t
RCD=
2*t
CK
, t
RAS=
5*t
CK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : t
CK=
7.5ns,
CL=2.5, BL=4, t
RCD=
3*t
CK
, t
RC=
9*t
CK
, t
RAS=
5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL=2,
BL=4, t
RCD
=3*t
CK
, t
RC
=9*t
CK
, t
RAS
=5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns, BL=4,
t
RCD
=10*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical
Case
:
V
CC
=2.5V, T=25C
2. Worst
Case
:
V
CC
=2.7V, T=10C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing
Patterns
:
DDR200 (100 MHz, CL=2) : t
CK
=10ns, CL2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : t
CK
=7.5ns,
CL=2.5, BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL2=2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=2*t
CK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
W3EG6464S-AD4
-BD4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
PACKAGE DIMENSIONS FOR AD4
ORDERING INFORMATION FOR AD4
Part Number
Speed
Height*
W3EG6464S335AD4
166MHz/333Mbps, CL=2.5
35.5 (1.38)*
W3EG6464S262AD4
133MHz/266Mbps, CL=2
35.5 (1.38)
W3EG6464S265AD4
133MHz/266Mbps, CL=2.5
35.5 (1.38)
W3EG6464S202AD4
100MHz/200Mbps, CL=2
35.5 (1.38)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
1.0 0.1
(0.039 0.004)
35.05
(1.138) MAX.
3.81
(0 .150) MAX.
2.31
(0.091) REF.
2.0
(0.079)
67.56
(2.666) MAX.
4.19
(0.165)
1.80
(0.071)
3.98
(0.157) MIN.
20
(0.787)
47.40
(1.866)
11.40
(0.449)
P1
3.98 0.1
(0.157 0.004)
* For DDR333 consult factory
W3EG6464S-AD4
-BD4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
PACKAGE DIMENSIONS FOR BD4
ORDERING INFORMATION FOR BD4
Part Number
Speed
Height*
W3EG6464S335BD4
166MHz/333Mbps, CL=2.5
31.75 (1.25)*
W3EG6464S262BD4
133MHz/266Mbps, CL=2
31.75 (1.25)
W3EG6464S265BD4
133MHz/266Mbps, CL=2.5
31.75 (1.25)
W3EG6464S202BD4
100MHz/200Mbps, CL=2
31.75 (1.25)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
U7
U5
67.56
(2.666) MAX
U1
U3
U9
R19
R17
R9
R2
R12
C3
C3
RP1
RP5
RP9
RP14
RP18
RP13
RP19
RP4
RP7
RP20
RP22
RP12
C5
C2
C6
C18
C7
C8 C26
R18
R5
R20
R10
R13
R14
R15
R16
R8
R7
R6
R4
C27
R11
C28
R21
C29
R3
1.0 0.1
(0.039 0.004)
3.81
(0.150) MAX.
2.31
(0.091) REF.
4.19
(0.165)
1.80
(0.071)
3.98
(0.157) MIN.
47.40
(1.866)
11.40
(0.449)
31.75
(1.25)
3.98 0.1
(0.157 0.004)
20
(0.787)
* For DDR333 consult factory
W3EG6464S-AD4
-BD4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2004
Rev. 1
PRELIMINARY
Document Title
512MB - 64Mx64, DDR, SDRAM UNBUFFERED w/PLL
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
7-21-03
Advanced
Rev 1
Corrected incidentals
(abreviations, symbols, etc.)
1.1 corrected pages 1-8
1.2 added AD4 and BD4 package options
1.3 added document title page
1.4 removed "ED" from part marking
3-4-04
Preliminary