White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY*

OPERATING FREQUENCIES

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

166MHz

133MHz

100MHz

CL-t

RCD

-t

2.5-3-3

2-2-2

2.5-3-3

2-2-2

1GB 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

FEATURES

Double-data-rate

architecture

DDR200, DDR266 and DDR333

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Serial presence detect

Dual

Rank

Power supply: 2.5V ± 0.20V

JEDEC standard 200 pin SO-DIMM package

· Package height options:

AD4: 35.5 mm (1.38") and
BD4: 31.75 mm (1.25")

NOTE: Consult factory for availability of:

· RoHS compliant products
· Vendor source control options
· Industrial temperature option

DESCRIPTION

The W3EG72128S is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. This module consists of eighteen 64Mx8 bit
DDR SDRAMs in 66 pin TSOP packages mounted on a
200 pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

REF

101

151

DQ42

REF

102

152

DQ46

DQ19

103

153

DQ43

DQ23

104

154

DQ47

DQ0

DQ24

105

155

DQ4

DQ28

106

156

DQ1

107

157

DQ5

108

158

DQ25

109

159

DQ29

110

160

DQS0

DQS3

111

161

DQM0

DQM3

112

162

DQ2

113

163

DQ48

DQ6

114

164

DQ52

DQ26

115

A10/AP

165

DQ49

DQ30

116

BA1

166

DQ53

DQ3

DQ27

117

BA0

167

DQ7

DQ31

118

RAS#

168

DQ8

119

WE#

169

DQS6

DQ12

120

CAS#

170

DQM6

CB0

121

CS0#

171

DQ50

CB4

122

CS1#

172

DQ54

DQ9

CB1

123

173

DQ13

CB5

124

174

DQS1

125

175

DQ51

DQM1

126

176

DQ55

DQS8

127

DQ32

177

DQ56

DQM8

128

DQ36

178

DQ60

DQ10

129

DQ33

179

DQ14

CB6

130

DQ37

180

DQ11

131

181

DQ57

DQ15

132

182

DQ61

CB3

133

DQS4

183

DQS7

CB7

134

DQM4

184

DQM7

CK0

135

DQ34

185

136

DQ38

186

CK0#

137

187

DQ58

138

188

DQ62

139

DQ35

189

DQ59

140

DQ39

190

DQ63

DQ16

141

DQ40

191

DQ20

142

DQ44

192

DQ17

143

193

SDA

DQ21

144

194

SA0

CKE1

145

DQ41

195

SCL

CKE0

146

DQ45

196

SA1

DQS2

147

DQS5

197

CCSPD

DQM2

148

DQM5

198

SA2

DQ18

A12

149

199

CCID

DQ22

100

A11

150

200

PIN CONFIGURATION

A0-A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

DQS0-DQS8

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock Input

CKE0, CKE1

Clock Enable input

CS0#, CS1#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQM0-DQM8

Data-In Mask

Power Supply (2.5V)

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply
(2.3V to 3.6V)

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

PIN NAMES

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

DQS2

DQM2

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS3

DQM3

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS8

DQM8

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS1

DQM1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS5

DQM5

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS6

DQM6

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQS7

DQM7

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS#

DQS

CS#

CS1#

CS0#

DQS0
DQM0

DQS4
DQM4

RAS#

CAS#

BA0-BA1

WE#

A0-A12

CKE0

CKE1

RAS: DDR SDRAMs

CAS: DDR SDRAMs

BA0-BA1: DDR SDRAMs

WE: DDR SDRAMs

A0-A12: DDR SDRAMs

CKE0: DDR SDRAMs

CKE1: DDR SDRAMs

SERIAL PD

SCL

SDA

SA0

SA1

SA2

DDR SDRAM

GND

120

PLL

CK0

CLK0/CLK0#

CLK1/CLK1#

CLK2/CLK2#

CLK3/CLK3#

CK0#

CK0A

CK0A#

FEEDBACK

Note: All datalines are terminated through a 22 ohms series resistor.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 to 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 to 3.6

Storage Temperature

STG

-55 to +150

°C

Power Dissipation

Short Circuit Current

Note:

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC CHARACTERISTICS

0°C

70°C, V

= 2.5V ± 0.2V

CAPACITANCE

= 25°C, f = 1MHz, V

= 3.3V, V

REF

=1.4V ± 200mV

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

CCQ/2

- 50mV

CCQ/2

+ 50mV

Termination Voltage

REF

- 0.04

REF

+ 0.04

Input High Voltage

REF

+ 0.15

CCQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Output High Voltage

+ 0.76

Output Low Voltage

- 0.76

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

Input Capacitance (RAS#, CAS#, WE#)

IN2

Input Capacitance (CKE0)

IN3

Input Capacitance (CK0,CK0#)

IN4

5.5

Input Capacitance (CS0#)

IN5

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

IDD SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Parameter

Symbol Conditions

DDR333@CL=2.5

Max

DDR266@CL=2

Max

DDR266@CL=2.5

Max

DDR200@CL=2

Max

Units

Operating Current

DD0

One device bank; Active - Precharge;
t

(MIN); t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.

2620

Operating Current

DD1

One device bank; Active-Read-
Precharge; Burst = 2; t

(MIN)

(MIN); Iout = 0mA; Address

and control inputs changing once per
clock cycle.

2890

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power- down
mode; t

(MIN); CKE=(low)

Idle Standby Current

DD2F

CS# = High; All device banks idle;
t

(MIN); CKE = high; Address

and other control inputs changing
once per clock cycle. Vin = Vref for
DQ, DQS and DM.

1085

Active Power-Down
Standby Current

DD3P

One device bank active; Power-down
mode; t

(MIN); CKE=(low)

630

Active Standby Current

DD3N

CS# = High; CKE = High; One
device bank; Active-Precharge;
t

RAS

(MAX); t

(MIN); DQ,

DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.

1175

Operating Current

DD4R

Burst = 2; Reads; Continous burst;
One device bank active;Address
and control inputs changing once
per clock cycle; t

(MIN); Iout

= 0mA.

2935

Operating Current

DD4W

Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t

(MIN); DQ,DM

and DQS inputs changing twice per
clock cycle.

3025

2845

Auto Refresh Current

DD5

(MIN)

4060

Self Refresh Current

DD6

CKE

0.2V

360

365

Operating Current

DD7A

Four bank interleaving Reads (BL=4)
with auto precharge with t

(MIN); t

(MIN); Address and

control inputs change only during
Active Read or Write commands.

5095

5050

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

DD1

: OPERATING CURRENT : ONE BANK

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

CK=

10ns, CL2,

BL=4, t

RCD=

2*t

, t

RAS=

5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

CK=

7.5ns,

CL=2.5, BL=4, t

RCD=

3*t

, t

RC=

9*t

, t

RAS=

5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL=2,

BL=4, t

RCD

=3*t

, t

=9*t

, t

RAS

=5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR333 (166MHz, CL=2.5) : t

=6ns, BL=4,

RCD

=10*t

, t

RAS

=7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: OPERATING CURRENT : FOUR BANKS

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

=10ns, CL2,

BL=4, t

RRD

=2*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL=2.5) : t

=7.5ns,

CL=2.5, BL=4, t

RRD

=3*t

, t

RCD

=3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL2=2,

BL=4, t

RRD

=2*t

, t

RCD

=2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR333 (166MHz, CL=2.5) : t

=6ns,

BL=4, t

RRD

=3*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

AC CHARACTERISTICS

335

262

265/202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.70

+0.70

-0.75

+0.75

-0.75

0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5

CK (2.5)

7.5

39, 44

CL = 2

CK (2)

7.5

7.5/10

39, 44

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per
access

DQSQ

0.4

0.5

22, 23

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.20

0.2

DQS falling edge from CK rising - hold time

DSH

0.20

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 36

Data-out low-impedance window from CK/CK#

-0.70

-0.75

16, 36

Address and control input hold time (fast slew rate)

IHF

0.75

0.90

Address and control input setup time (fast slew rate)

ISF

0.75

0.90

Address and control input hold time (slow slew rate)

IHS

0.8

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

AC CHARACTERISTICS

335

262

265/202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Address and control input setup time (slow slew rate)

ISS

0.8

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

HP -

QHS

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.50

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

30, 47

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

Notes
1.

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related specifi cations
and device operation are guaranteed for the full voltage range specifi ed.

Outputs measured with equivalent load:

Output

Output
(V

OUT

)

Reference

Point

30pF

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test

environment, but input timing is still referenced to V

REF

(or to the crossing point for

CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

CCQ/2

of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (non-common mode) on V

REF

may

not exceed ±2 percent of the DC value. Thus, from V

CCQ/2

, V

REF

is allowed ±25mV

for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest V

REF

bypass capacitor.

7. V

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

and must track variations

in the DC level of V

REF

8. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with mini-mum cycle time at CL = 2 for 262, and 263, CL = 2.5 for 335 and 265 with
the outputs open.

Enables on-chip refresh and address counters.

10. I

specifi cations are tested after the device is properly initialized, and is averaged

at the defi ned cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V, V

REF

= VSS,

f = 100 MHz, T

= 25°C, V

OUT

(DC) = V

CCQ/2

, V

OUT

(peak to peak) = 0.2V. DM input

is grouped with I/O pins, refl ecting the fact that they are matched in loading.

12. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing

must be derated: t

has an additional 50ps per each 100 mV/ns reduction in slew

rate from 500mV/ns, while t

is unaffected. If the slew rate exceeds 4.5 V/ns,

functionality is uncertain. For 335, slew rates must be 0.5 V/ns.

13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK and CK# cross; the input reference level for signals other than CK/CK# is
V

REF

14. Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the period

before V

REF

stabilizes, CKE < 0.3 x V

CCQ

is recognized as LOW.

15. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is V

16. t

and t

transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).

17. The intent of the Don't Care state after completion of the postamble is the DQS-

driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above V

DC (MIN) then it must not transition low (below V

DC) prior to t

DQSH

(MIN).

18. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t

DQSS

20. MIN

or t

RFC

) for I

measurements is the smallest multiple of t

that meets

the minimum absolute Value for the respective parameter. t

RAS

(MAX) for I

measurements is the largest multiple of t

that meets the maximum absolute value

for t

RAS

21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125µs.

However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.

22. The valid data window is derived by achieving other specifi cations: t

/2),

DQSQ

, and t

= t

- t

QHS

). The data valid window derates directly porportional

with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, beyon which functionality
is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty
cycles ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (t

RFC

[MIN]) else CKE is LOW (i.e., during

standby).

25. To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through to the target AC

level, V

(AC) or V

(AC).Reach at least the target AC level.

b. After the AC target level is reached, continue to maintain at least the target DC

level, V

(DC) or V

(DC).

26. JEDEC specifi es CK and CK# input slew rate must be 1V/ns (2V/ns

differentially).

27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.

If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps
must be added to t

and t

for each 100mv/ns reduction in slew rate. If slew rate

exceeds 4V/ns, functionality is uncertain. For 335, slew rates must be 0.5 V/ns.

28. V

must not vary more than 4 percent if CKE is not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary

by the same amount. t

min is the lesser of t

minimum and t

minimum actually

applied to the device CK and CK# inputs, collectively during bank active.

30. READs and WRITEs with auto precharge are not allowed to be issued until

RAS

(MIN) can be satisfi ed prior to the internal precharge command being issued.

31. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either -300mV or 2.2V, whichever is more positive.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005
Rev. 3

PRELIMINARY

32. Normal Output Drive Curves:

a. The full variation in driver pull-down current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 8, Pull-Down Characteristics.

b. The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 9, Pull-Up Characteristics.

d. The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.

f. The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10 percent, for device drain-to-source volt-ages from 0.1V to 1.0V.

33. The voltage levels used are derived from a mini-mum V

level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signifi cantly different voltage values.

34. V

overshoot: V

(MAX) = V

Q + 1.5V for a pulse width !5 3ns and the pulse

width can not be greater than 1/3 of the cycle rate. V

undershoot: V

(MIN) =

-1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the
cycle rate.

35. V

and V

Q must track each other.

36. t

(MAX) will prevail over t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN) will

prevail over t

DQSCK

(MIN) + t

RPRE

(MAX) condition.

37. t

RPST

end point and t

RPRE

begin point are not referenced to a specifi c voltage level

but specify when the device output is no longer driving (t

RPST

), or begins driving

RPRE

38. During Initialization, V

CCQ

, V

, and V

REF

must be equal to or less than V

+ 0.3V.

Alternatively, V

may be 1.35V maximum during power up, even if V

CCQ

are

0.0V, provided a minimum of 42 0 of series resistance is used between the V

supply and the input pin.

39. The current part operates below the slowest JEDEC operating frequency of 83

MHz. As such, future die may not refl ect this option.

40.

Random addressing changing and 50 percent of data changing at every transfer.

41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.

43. I

2N specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.

2Q is similar to I

2F except I

2Q specifi es the address and control inputs to

remain stable. Although I

2F, I

2N, and I

2Q are similar, I

2F is "worst case."

44. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.

45. Leakage number refl ects the worst case leakage possible through the module pin,

not what each memory device contributes.

46. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or

LOW.

47. The 335 speed grade will operate with t

RAS

(MIN) = 40ns and t

RAS

(MAX) =

120,000ns at any slower frequency.

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