White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

FEATURES

Double-data-rate architecture
DDR200 and DDR266
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V ± 0.20V
184 pin DIMM package

· D3 = 26.67 (1.05")

Note: Consult factory for availability of lead-free products (F = Lead-Free, G = RoHS

compliant)

128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL

DESCRIPTION

The W3EG7217S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and burst lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

* This product is subject to change without notice.

OPERATING FREQUENCIES

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

133MHz

100MHz

CL-t

RCD

-t

2-2-2

2.5-3-3

2-2-2

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

PIN CONFIGURATION

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

REF

DQS8

139

DQ0

DQ4

140

DQM8

CB2

DQ5

141

A10

DQ1

CCQ

142

CB6

DQS0

CB3

DQM0

143

CCQ

DQ2

BA1

DQ6

144

CB7

DQ32

DQ7

145

DQ3

100

146

DQ36

DQ33

101

147

DQ37

RESET#

DQS4

102

148

DQ34

103

149

DQM4

DQ8

104

CCQ

150

DQ38

DQ9

BA0

105

DQ12

151

DQ39

DQS1

DQ35

106

DQ13

152

CCQ

DQ40

107

DQM1

153

DQ44

*CK1

CCQ

108

154

RAS#

*CK1#

WE#

109

DQ14

155

DQ45

DQ41

110

DQ15

156

CCQ

DQ10

CAS#

111

CKE1*

157

CS0#

DQ11

112

CCQ

158

CS1#*

CKE0

DQS5

113

*BA2

159

DQM5

CCQ

DQ42

114

DQ20

160

DQ16

DQ43

115

A12

161

DQ46

DQ17

116

162

DQ47

DQS2

*CS2#

117

DQ21

163

A13*

DQ48

118

A11

164

CCQ

DQ49

119

DQM2

165

DQ52

DQ18

120

166

DQ53

*CK2#

121

DQ22

167

A13

CCQ

*CK2

122

168

DQ19

CCQ

123

DQ23

169

DQM6

DQS6

124

170

DQ54

DQ24

DQ50

125

171

DQ55

DQ51

126

DQ28

172

CCQ

DQ25

127

DQ29

173

DQS3

CCID

128

CCQ

174

DQ60

DQ56

129

DQM3

175

DQ61

DQ57

130

176

DQ26

131

DQ30

177

DQS16

DQ27

DQS7

132

178

DQ62

DQ58

133

DQ31

179

DQ63

DQ59

134

CB4

180

CCQ

135

CB5

181

SA0

CB0

136

CCQ

182

SA1

CB1

SDA

137

CK0

183

SA2

SCL

138

CK0#

184

CCSPD

PIN NAMES

A0-A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check bits

DQS0-DQS8

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock input

CKE0

Clock Enable input

CS0#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQM0-DQM8

Data-In Mask

Power Supply

CCQ

Power Supply for DQS

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

RESET#

Reset Enable

* Not Used

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

FUNCTIONAL BLOCK DIAGRAM

NOTE: All resistor values are 22ohms unless otherwise specified.

SA0

SERIAL PD

SDA

SA1

SA2

CS0#

BA0, BA1

A0-A12

RAS#

RCS0#

RBA0, RBA1: DDR SDRAMS

RA0-RA12: DDR SDRAMS

RRAS#: DDR SDRAMS

RCAS#: DDR SDRAMS

RCKE0: DDR SDRAMS

RWE#: DDR SDRAMS

RESET#

CAS#

CKE0

WE#

CK#

REF

DDR SDRAMS

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM0

CS0#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

R
E

S
T
E

PLL

DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2

SCL

DM CS# DQS

DQS0

DQM4

DQS4

DQM1

DQS1

DQM5

DQS5

DQM2

DQS2

DQM6

DQS6

DM CS# DQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DM CS# DQS

DQM3

DQS3

DQM7

DQS7

DQM8

DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CCQ

DDR SDRAMS

CK0
CK0#

120

SPD

CCSPD

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 ~ 3.6

Storage Temperature

STG

-55 ~ +150

°C

Power Dissipation

Short Circuit Current

Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC CHARACTERISTICS

= 0°C to 70°C, V

= 2.5V ± 0.2V

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

1.15

1.35

Termination Voltage

1.15

1.35

Input High Voltage

REF

+0.15

CCQ

+0.3

Input Low Voltage

-0.3

REF

+0.15

Output High Voltage

+0.76

Output Low Voltage

-0.76 V

CAPACITANCE

= 25°C, f = 1MHz, V

= 2.5V

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

6.25

Input Capacitance (RAS#,CAS#,WE#)

IN2

6.25

Input Capacitance (CKE0)

IN3

6.25

Input Capacitance (CK0#,CK0)

IN4

5.5

Input Capacitance (CS0#)

IN5

6.25

Input Capacitance (DQM0-DQM8)

IN6

8.0

Input Capacitance (BA0-BA1)

IN7

6.25

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

8.0

Data input/output capacitance (CB0-CB7)

OUT

8.0

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes PLL and Register Power

Parameter

Symbol

Conditions

DDR266@CL = 2

Max

DDR266@CL = 2.5

Max

DDR200@CL = 2

Max

Units

Operating Current

DD0

One device bank; Active = Precharge; t

= t

(MIN); t

(MIN); DQ,DM and DQS inputs changing once per clock

cycle; Address and control inputs changing once every two
cycles.

1266

1221

Operating Current

DD1

One device bank; Active-Read-Precharge; Burst = 2; t

(MIN);t

= t

(MIN); Iout = 0mA; Address and control

inputs changing once per clock cycle.

1356

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power- down mode; t

= t

(MIN);

CKE = (low)

dle Standby Current

DD2F

CS# = High; All device banks idle; t

= t

(MIN); CKE =

high; Address and other control inputs changing once per
clock cycle. V

= V

REF

for DQ, DQS and DM.

750

705

Active Power-Down
Standby Current

DD3P

One device bank active; Power-down mode; t

(MIN); CKE

= (low)

225

180

Active Standby Current

DD3N

CS# = High; CKE = High; One device bank; Active-
Precharge; t

= t

RAS

(MAX); t

= t

(MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.

795

750

Operating Current

DD4R

Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t

= t

(MIN); I

OUT

= 0mA.

1446

1401

Operating Current

DD4W

Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t

= t

(MIN); DQ,DM and DQS inputs changing twice per

clock cycle.

1401

1356

Auto Refresh Current

DD5

= t

(MIN)

2325

Self Refresh Current

DD6

CKE

0.2V

372

363

Operating Current

DD7A

Four bank interleaving Reads (BL = 4) with auto precharge
with t

= t

(MIN); t

= t

(MIN); Address and control

inputs change only during Active Read or Write commands.

3246

3201

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes DDR SDRAM Component Only

Parameter

Symbol

Conditions

DDR266@CL = 2

Max

DDR266@CL = 2.5

Max

DDR200@CL = 2

Max

Units

Operating Current

DD0

One device bank; Active = Precharge; t

= t

(MIN); t

(MIN); DQ,DM and DQS inputs changing once per clock

cycle; Address and control inputs changing once every two
cycles.

900

945

Operating Current

DD1

One device bank; Active-Read-Precharge; Burst = 2; t

(MIN);t

= t

(MIN); Iout = 0mA; Address and control

inputs changing once per clock cycle.

1080

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power- down mode; t

= t

(MIN);

CKE = (low)

dle Standby Current

DD2F

CS# = High; All device banks idle; t

= t

(MIN); CKE =

high; Address and other control inputs changing once per
clock cycle. V

= V

REF

for DQ, DQS and DM.

405

360

Active Power-Down
Standby Current

DD3P

One device bank active; Power-down mode; t

(MIN); CKE

= (low)

225

180

Active Standby Current

DD3N

CS# = High; CKE = High; One device bank; Active-
Precharge; t

= t

RAS

(MAX); t

= t

(MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.

450

405

Operating Current

DD4R

Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t

= t

(MIN); I

OUT

= 0mA.

1170

1125

Operating Current

DD4W

Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t

= t

(MIN); DQ,DM and DQS inputs changing twice per

clock cycle.

1125

1080

Auto Refresh Current

DD5

= t

(MIN)

1980

Self Refresh Current

DD6

CKE

0.2V

Operating Current

DD7A

Four bank interleaving Reads (BL = 4) with auto precharge
with t

= t

(MIN); t

= t

(MIN); Address and control

inputs change only during Active Read or Write commands.

2970

2925

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

DD1

: OPERATING CURRENT : ONE BANK

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

CK=

10ns, CL2,

BL=4, t

RCD=

2*t

, t

RAS=

5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

CK=

7.5ns,

CL=2.5, BL=4, t

RCD=

3*t

, t

RC=

9*t

, t

RAS=

5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL=2,

BL=4, t

RCD

=3*t

, t

=9*t

, t

RAS

=5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: OPERATING CURRENT : FOUR BANKS

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

=10ns, CL2,

BL=4, t

RRD

=2*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL=2.5) : t

=7.5ns,

CL=2.5, BL=4, t

RRD

=3*t

, t

RCD

=3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL2=2,

BL=4, t

RRD

=2*t

, t

RCD

=2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3

R (0-3) = Read Bank 0-3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

262/265

202

Parameter

Symbol

Min

Max

Min

Max

Units

Notes

Access window of DQs from CK, CK#

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

(2.5)

7.5

CL=2

(2)

7.5/10

DQ and DM input hold time relative to DQS

0.5

0.6

14,17

DQ and DM input setup time relative to DQS

0.5

0.6

14,17

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK, CK#

DQSCK

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.5

0.6

13,14

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

, t

Data-out high-impedance window from CK, CK#

+0.75

+0.8

8,19

Data-out low-impedance window from CK, CK#

-0.75

-0.8

8,20

Address and control input hold time (fast slew rate)

IHf

0.90

1.1

Address and control input set-up time (fast slew rate)

ISf

0.90

1.1

Address and control input hold time (slow slew rate)

IHs

1.1

Address and control input setup time (slow slew rate)

ISs

1.1

Address and control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

-t

QHS

-t

QHS

13,14

Data hold skew factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

262/265

202

Parameter

Symbol

Min

Max

Min

Max

Units

Notes

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

10,11

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

-t

DQSQ

-t

DQSQ

REFRESH to REFRESH command interval

REFC

140.6

Average periodic refresh interval

REFI

15.6

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

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White Electronic Designs

W3EG7217S-D3

December 2004
Rev. 1

11.

It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t

DQSS

12. The refresh period is 64ms. This equates to an average refresh

rate of 15.625µs. However, an AUTO REFRESH command must
be asserted at least once every 140.6µs; burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is
not allowed.

13. The valid data window is derived by achieving other specifi cations

- t

CK/2

), t

DQSQ

, and t

= t

- t

QHS

). The data valid

window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.

14. Referenced to each output group: x8 = DQS with DQ0-DQ7.

15. READs and WRITEs with auto precharge are not allowed to be

issued until t

RAS

(MIN) can be satisfi ed prior to the internal precharge

command being issued.

16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns

(2V/ns differentially).

17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t

and t

for

each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.

18. t

min is the lesser of t

min and t

min actually applied to the

device CK and CK# inputs, collectively during bank active.

19. t

(MAX) will prevail over the t

DQSCK

(MAX) + t

RPST

(MAX)

condition. t

(MIN) will prevail over t

DQSCK

(MIN) + PRE (MAX)

condition.

20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.

21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t

RFC

has been satisfi ed.

22. Whenever the operating frequency is altered, not including jitter,

the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).

Notes

All voltages referenced to V

2. Tests

for

timing,

, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but
the related specifi cations and device operations are guaranteed for
the full voltage range specifi ed.

Outputs are measured with equivalent load:

Output

Output
(V

OUT

)

Reference

Point

30pF

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V

in the test environment, but input timing is still referenced to V

REF

(or to the crossing point for CK/CK#), and parameter specifi cations
are guaranteed for the specifi ed AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are defi ned in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).

For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: t

has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. t

has 0ps added, that is, it remains constant.

If the slew rate exceeds 4.5V/ns, functionality is uncertain. For
266, slew rates must be greater than or equal to 0.5V/ns.

Inputs are not recognized as valid until V

REF

stabilizes. Exception:

during the period before V

REF

stabilizes, CKE

0.3 x V

CCQ

recognized as LOW.

8. t

and t

transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a
specifi c voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).

The intent of the "Don't Care" state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above V

IHDC

(MIN) then it must not transition

LOW (below V

IHDC

) prior to t

DQSH

(MIN).

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus
turnaround.

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