White Electronic Designs

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

W3EG72256S-JD3

-AJD3

PRELIMINARY*

FEATURES

Double-data-rate architecture
DDR200, DDR266 and DDR333:

· JEDEC design specifi cations

Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: V

= 2.5V ± 0.20V

JEDEC standard 184 pin DIMM package

· Package height option:

JD3: 30.48mm (1.20")
AJD3: 28.70mm (1.13")

· Consult factory for availability of lead-free

products.

DESCRIPTION

The W3EG72256S is a 256Mx72 Double Data Rate
SDRAM memory module based on 1Gb DDR SDRAM
components. The module consists of eighteen 1Gb DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL

OPERATING FREQUENCIES

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

166MHz

133MHz

100MHz

CL-t

RCD

-t

2.5-3-3

2-2-2

2-3-3

2.5-3-3

2-2-2

Advance information: Speed may not be available.

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

REF

DQS8

139

DQ0

DQ4

140

DQS17

CB2

DQ5

141

A10

DQ1

CCQ

142

CB6

DQS0

CB3

DQS9

143

CCQ

DQ2

BA1

DQ6

144

CB7

DQ32

DQ7

145

DQ3

CCQ

100

146

DQ36

DQ33

101

147

DQ37

RESET#

DQS4

102

148

DQ34

103

149

DQS13

DQ8

104

CCQ

150

DQ38

DQ9

BA0

105

DQ12

151

DQ39

DQS1

DQ35

106

DQ13

152

CCQ

DQ40

107

DQS10

153

DQ44

CCQ

108

154

RAS#

WE#

109

DQ14

155

DQ45

DQ41

110

DQ15

156

CCQ

DQ10

CAS#

111

CKE1

157

CS0#

DQ11

112

CCQ

158

CKE0

DQS5

113

159

DQS14

CCQ

DQ42

114

DQ20

160

DQ16

DQ43

115

A12

161

DQ46

DQ17

116

162

DQ47

DQS2

117

DQ21

163

DQ48

118

A11

164

CCQ

DQ49

119

DQS11

165

DQ52

DQ18

120

166

DQ53

121

DQ22

167

A13

CCQ

122

168

DQ19

CCQ

123

DQ23

169

DQS15

DQS6

124

170

DQ54

DQ24

DQ50

125

171

DQ55

DQ51

126

DQ28

172

CCQ

DQ25

127

DQ29

173

DQS3

CCID

128

CCQ

174

DQ60

DQ56

129

DQS12

175

DQ61

DQ57

130

176

DQ26

131

DQ30

177

DQS16

DQ27

DQS7

132

178

DQ62

DQ58

133

DQ31

179

DQ63

DQ59

134

CB4

180

CCQ

135

CB5

181

SA0

CB0

136

CCQ

182

SA1

CB1

SDA

137

CK0

183

SA2

SCL

138

CK0#

184

CCSPD

PIN CONFIGURATION

A0-A13

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check bits

DQS0-DQS17

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock Input

CKE0, CKE1

Clock Enable input

CS0#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

Power Supply

CCQ

Power Supply for DQS

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

RESET#

Reset Enable

PIN NAMES

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W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

WE#

CKE1

CKE0

CAS#

RAS#

A0-A13

BA0-BA1

CS0#

CKO SDRAM

RCS0#

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

R
E
G

S
T
E
R

DQ0
DQ1
DQ2
DQ3

DQ8
DQ9

DQ10
DQ11

DQ16
DQ17
DQ18
DQ19

DQ24
DQ25
DQ26
DQ27

DQ32
DQ33
DQ34
DQ35

DQ40
DQ41
DQ42
DQ43

DQ48
DQ49
DQ50
DQ51

DQ56
DQ57
DQ58
DQ59

CB0
CB1
CB2
CB3

RESET#

PCK#

PCK

RCS0#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

DQS0

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

DQ4
DQ5
DQ6
DQ7

DQ12
DQ13
DQ14
DQ15

DQ20
DQ21
DQ22
DQ23

DQ28
DQ29
DQ30
DQ31

DQ36
DQ37
DQ38
DQ39

DQ44
DQ45
DQ46
DQ47

DQ52
DQ53
DQ54
DQ55

DQ60
DQ61
DQ62
DQ63

CB4
CB5
CB6
CB7

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

I/O 3
I/O 2
I/O 1
I/O 0

DQS

CS#

DQS9

CCSPD

CCQ

REF

SPD

DDR SDRAMs

RBA0 - RBA1
RA0 - RA13
RRAS#
RCAS#
RCKE0
RCKE1
RWE#

DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs

Serial PD

SA0 SA1

SA2

SDA

CKO#

PLL

SCL

Notes:
1.

DQ-to-I/O wiring is shown as
recommended but may be changed.

2. DQ/DQS/DM/CKE/S

relationships

must be maintained as shown.

NOTE: All resistor values are 22 ohms unless otherwise specifi ed

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 to 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 to 3.6

Storage Temperature

STG

-55 to +150

°C

Power Dissipation

Short Circuit Current

Note:

Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability

ABSOLUTE MAXIMUM RATINGS

DC CHARACTERISTICS

0°C

70°C, V

= 2.5V ± 0.2V

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

1.15

1.35

Termination Voltage

1.15

1.35

Input High Voltage

REF

+ 0.15

CCQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Output High Voltage

+ 0.76

Output Low Voltage

-0.76

CAPACITANCE

= 25°C. f = 1MHz, V

= 2.5V ± 0.2V

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A13)

IN1

6.25

Input Capacitance (RAS#,CAS#,WE#)

IN2

6.25

Input Capacitance (CKE0)

IN3

6.25

Input Capacitance (CK0#,CK0)

IN4

5.5

Input Capacitance (CS0#)

IN5

6.25

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

6.25

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

Data input/output capacitance (CB0-CB7)

OUT

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR333@CL=2.5*

Max

DDR266@CL=2, 2.5

Max

DDR200@CL=2

Max

Units

Operating Current

DD0

One device bank; Active - Precharge;
t

(MIN); t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.

2880

2610

Operating Current

DD1

One device bank; Active-Read-
Precharge Burst = 2; t

(MIN);

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per
clock cycle.

3510

3240

Precharge Power-
Down Standby
Current

DD2P

All device banks idle; Power-down
mode; t

(MIN); CKE=(low)

180

rnA

Idle Standby Current

DD2F

CS# = High; All device banks idle;
t

(MIN); CKE = high; Address

and other control inputs changing
once per clock cycle. V

= V

REF

for

DQ, DQS and DM.

1170

1080

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down
mode; t

(MIN); CKE=(low)

630

540

Active Standby
Current

DD3N

CS# = High; CKE = High; One device
bank; Active-Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.

900

810

Operating Current

DD4R

Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T

= T

(MIN); l

OUT

= 0mA.

3960

3600

Operating Current

DD4W

Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle.

4140

3780

rnA

Auto Refresh
Current

DD5

= t

(MIN)

6120

5940

Self Refresh Current

DD6

CKE

0.2V

162

Operating Current

DD7A

Four bank interleaving Reads (BL=4)
with auto precharge with t

(MIN); t

(MIN); Address and

control inputs change only during
Active Read or Write commands.

9450

8730

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes PLL and register power

Parameter

Symbol

Conditions

DDR333@CL=2.5*

Max

DDR266@CL=2, 2.5

Max

DDR200@CL=2

Max

Units

Operating Current

DD0

One device bank; Active - Precharge;
t

(MIN); t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.

3155

2885

Operating Current

DD1

One device bank; Active-Read-
Precharge Burst = 2; t

(MIN);

(MIN); l

OUT

= 0mA; Address

and control inputs changing once per
clock cycle.

3785

3515

Precharge Power-
Down Standby
Current

DD2P

All device banks idle; Power-down
mode; t

(MIN); CKE=(low)

180

rnA

Idle Standby Current

DD2F

CS# = High; All device banks idle;
t

(MIN); CKE = high; Address

and other control inputs changing
once per clock cycle. V

= V

REF

for

DQ, DQS and DM.

1480

1390

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down
mode; t

(MIN); CKE=(low)

630

540

Active Standby
Current

DD3N

CS# = High; CKE = High; One device
bank; Active-Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.

1210

1120

Operating Current

DD4R

Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T

= T

(MIN); l

OUT

= 0mA.

4235

3875

Operating Current

DD4W

Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t

(MIN); DQ,DM

and DQS inputs changing once per
clock cycle.

4415

4055

rnA

Auto Refresh
Current

DD5

= t

(MIN)

6430

6250

Self Refresh Current

DD6

CKE

0.2V

472

Operating Current

DD7A

Four bank interleaving Reads (BL=4)
with auto precharge with t

(MIN); t

(MIN); Address and

control inputs change only during
Active Read or Write commands.

9725

9005

White Electronic Designs

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-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

DD1

: Operating Current : One Bank

1. Typical

Case

= 2.5V, T = 25°C

2. Worst

Case

= 2.7V, T = 10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL = 2) : t

= 10ns, CL2,

BL=4, t

RCD

= 2*t

, t

RAS

= 5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

= 7.5ns,

CL = 2.5, BL = 4, t

RCD

= 3*tCK, t

= 9*t

RAS

= 5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL = 2) : t

= 7.5ns,

CL = 2, BL = 4, t

RCD

= 3*t

, t

= 9*t

RAS

= 5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR333 (166MHz, CL = 2.5) : t

= 6ns,

BL = 4, t

RCD

= 10*t

, t

RAS

= 7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: Operating Current: Four Banks

1. Typical

Case

= 2.5V, T = 25°C

2. Worst

Case

= 2.7V, T = 10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. I

OUT

=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL = 2) : t

= 10ns, CL2,

BL = 4, t

RRD

= 2*t

, t

RCD

= 3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL = 2.5) : t

= 7.5ns,

CL = 2.5, BL = 4, t

RRD

= 3*t

, t

RCD

= 3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL = 2) : t

= 7.5ns,

CL2 = 2, BL = 4, t

RRD

= 2*t

, t

RCD

= 2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR333 (166MHz, CL=2.5) : t

=6ns,

BL=4, t

RRD

=3*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262/263/265

202

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

Access window of DQs from CK, CK#

-0.7

+0.7

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

(2.5)

7.5

CL=2

(2)

7.5

DQ and DM input hold time relative to DQS

0.45

0.5

0.6

14,17

DQ and DM input setup time relative to DQS

0.45

0.5

0.6

14,17

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK, CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.45

0.5

13,14

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

, t

Data-out high-impedance window from CK, CK#

+0.70

+0.75

+0.8

8,19

Data-out low-impedance window from CK, CK#

-0.70

-0.75

-0.8

8,20

Address and control input hold time (fast slew rate)

IHf

0.75

0.90

1.1

Address and control input set-up time (fast slew rate)

ISf

0.75

0.90

1.1

Address and control input hold time (slow slew rate)

IHs

0.80

1.1

Address and control input setup time (slow slew rate)

ISs

0.80

1.1

Address and control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

-t

QHS

-t

QHS

-t

QHS

13,14

Data hold skew factor

QHS

0.55

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

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W3EG72256S-JD3

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White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262/263/265

202

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

10,11

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

-t

DQSQ

-t

DQSQ

-t

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

Average periodic refresh interval

REFI

7.8

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

126

127.5

Exit SELF REFRESH to READ command

XSRD

200

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

11.

It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t

DQSS

12. The refresh period is 64ms. This equates to an average refresh

rate of 7.8125µs. However, an AUTO REFRESH command must
be asserted at least once every 70.3µs; burst refreshing or posting
by the DRAM controller greater than eight refresh cycles is not
allowed.

13. The valid data window is derived by achieving other specifi cations

- t

CK/2

), t

DQSQ

, and t

= t

- t

QHS

). The data valid

window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.

14. Referenced to each output group: x4 = DQS with DQ0-DQ3.

15. READs and WRITEs with auto precharge are not allowed to be

issued until t

RAS

(MIN) can be satisfi ed prior to the internal precharge

command being issued.

16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns

(2V/ns differentially).

17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t

and t

for

each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.

18. t

min is the lesser of t

min and t

min actually applied to the

device CK and CK# inputs, collectively during bank active.

19. t

(MAX) will prevail over the t

DQSCK

(MAX) + t

RPST

(MAX)

condition. t

(MIN) will prevail over t

DQSCK

(MIN) + PRE (MAX)

condition.

20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.

21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t

RFC

has been satisfi ed.

22. Whenever the operating frequency is altered, not including jitter,

the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).

Notes

All voltages referenced to V

2. Tests

for

timing,

, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but
the related specifi cations and device operations are guaranteed for
the full voltage range specifi ed.

Outputs are measured with equivalent load:

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V

in the test environment, but input timing is still referenced to V

REF

(or to the crossing point for CK/CK#), and parameter specifi cations
are guaranteed for the specifi ed AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are defi ned in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).

For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: t

has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. t

has 0ps added, that is, it remains constant.

If the slew rate exceeds 4.5V/ns, functionality is uncertain. For
335, slew rates must be greater than or equal to 0.5V/ns.

Inputs are not recognized as valid until V

REF

stabilizes. Exception:

during the period before V

REF

stabilizes, CKE

0.3 x V

CCQ

recognized as LOW.

8. t

and t

transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a
specifi c voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).

The intent of the "Don't Care" state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above V

IHDC

(MIN) then it must not transition

LOW (below V

IHDC

) prior to t

DQSH

(MIN).

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus
turnaround.

Output

OUT

)

Reference

Point

30pF

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

2.31

(0.091)

(2x)

133.48

(5.255" MAX.)

3.99

(0.157 (2x))

17.78

(0.700)

10.01

(0.394)

6.35

(0.250)

64.77

(2.550)

1.78

(0.070)

49.53

(1.950)

3.00

(0.118)

(4x)

30.48

(1.20 MAX)

1.27

(0.050 TYP.)

6.35

(0.250)

128.95

(5.077")

131.34

(5.171")

3.81

(0.150 MAX)

3.99

(0.157)

(MIN)

1.27 ± 0.10

(0.050 ± 0.004)

PACKAGE DIMENSIONS FOR JD3

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR JD3

Part Number

Speed

CAS Latency

RCD

Height*

W3EG72256S335JD3

166MHz/133Mb/s

2.5

30.48 (1.20")

W3EG72256S262JD3

133MHz/266Mb/s

30.48 (1.20")

W3EG72256S263JD3

133MHz/266Mb/s

30.48 (1.20")

W3EG72256S265JD3

133MHz/266Mb/s

2.5

30.48 (1.20")

W3EG72256S202JD3

100MHz/200Mb/s

30.48 (1.20")

Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)
Vendor Code: M = Micron, S = Samsung

White Electronic Designs

W3EG72256S-JD3

-AJD3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

December 2004
Rev. 2

PRELIMINARY

133.48

(5.255" MAX.)

3.99

(0.157 (2x))

17.78

(0.700)

10.01

(0.394)

6.35

(0.250)

64.77

(2.550)

1.78

(0.070)

49.53

(1.950)

3.00

(0.118)

(4x)

28.70

(1.13 MAX)

2.31

(0.091)

(2x)

1.27

(0.050 TYP.)

6.35

(0.250)

128.95

(5.077")

131.34

(5.171")

3.81

(0.150 MAX)

3.99

(0.157)

(MIN)

1.27 ± 0.10

(0.050 ± 0.004)

PACKAGE DIMENSIONS FOR AJD3

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR AJD3

Part Number

Speed

CAS Latency

RCD

Height*

W3EG72256S335AJD3

166MHz/133Mb/s

2.5

28.70 (1.13")

W3EG72256S262AJD3

133MHz/266Mb/s

28.70 (1.13")

W3EG72256S263AJD3

133MHz/266Mb/s

28.70 (1.13")

W3EG72256S265AJD3

133MHz/266Mb/s

2.5

28.70 (1.13")

W3EG72256S202AJD3

100MHz/200Mb/s

28.70 (1.13")

Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)
Vendor Code: M = Micron, S = Samsung

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W3EG72256S263AJD3