1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2005
Rev. 3
PRELIMINARY*
W3EG7262S-D3
-JD3
FEATURES
Double-data-rate architecture
DDR200 and DDR266
JEDEC design specifi ed
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual
Rank
Power supply: 2.5V 0.2V
JEDEC184 pin DIMM package
JD3 PCB height: 30.48mm (1.20")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
512MB 2X32Mx72 DDR SDRAM UNBUFFERED
DESCRIPTION
The W3EG7262S is a 2x32Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eighteen 32Mx8
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
133MHz
133MHz
100MHz
CL-t
RCD
-t
RP
2-2-2
2.5-3-3
2-2-2
W3EG7262S-D3
-JD3
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2005
Rev. 3
PRELIMINARY
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
REF
47
DQS8
93
V
SS
139
V
SS
2
DQ0
48
A0
94
DQ4
140
DQM8
3
V
SS
49
CB2
95
DQ5
141
A10
4
DQ1
50
V
SS
96
V
CCQ
142
CB6
5
DQS0
51
CB3
97
DQM0
143
V
CCQ
6
DQ2
52
BA1
98
DQ6
144
CB7
7
V
CC
53
DQ32
99
DQ7
145
V
SS
8
DQ3
54
V
CCQ
100
V
SS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
NC
56
DQS4
102
NC
148
V
CC
11
V
SS
57
DQ34
103
NC
149
DQM4
12
DQ8
58
V
SS
104
V
CCQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
V
SS
15
V
CCQ
61
DQ40
107
DQM1
153
DQ44
16
CK1
62
V
CCQ
108
V
CC
154
RAS#
17
CK1#
63
WE#
109
DQ14
155
DQ45
18
V
SS
64
DQ41
110
DQ15
156
V
CCQ
19
DQ10
65
CAS#
111
CKE1
157
CS0#
20
DQ11
66
V
SS
112
V
CCQ
158
CS1#
21
CKE0
67
DQS5
113
NC
159
DQM5
22
V
CCQ
68
DQ42
114
DQ20
160
V
SS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
V
CC
116
V
SS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
26
V
SS
72
DQ48
118
A11
164
V
CCQ
27
A9
73
DQ49
119
DQM2
165
DQ52
28
DQ18
74
V
SS
120
V
CC
166
DQ53
29
A7
75
CK2#
121
DQ22
167
NC
30
V
CCQ
76
CK2
122
A8
168
V
CC
31
DQ19
77
V
CCQ
123
DQ23
169
DQM6
32
A5
78
DQS6
124
V
SS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
V
SS
80
DQ51
126
DQ28
172
V
CCQ
35
DQ25
81
V
SS
127
DQ29
173
NC
36
DQS3
82
V
CCID
128
V
CCQ
174
DQ60
37
A4
83
DQ56
129
DQM3
175
DQ61
38
V
CC
84
DQ57
130
A3
176
V
SS
39
DQ26
85
V
CC
131
DQ30
177
DQM7
40
DQ27
86
DQS7
132
V
SS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
V
SS
88
DQ59
134
CB4
180
V
CCQ
43
A1
89
V
SS
135
CB5
181
SA0
44
CB0
90
NC
136
V
CCQ
182
SA1
45
CB1
91
SDA
137
CK0
183
SA2
46
V
CC
92
SCL
138
CK0#
184
V
CCSPD
PIN CONFIGURATION
A0-A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check bits
DQS0-DQS8
Data Strobe Input/Output
CK0, CK1, CK2
Clock Input
CK0#, CK1#, CK2#
Clock Input
CKE0, CKE1
Clock Enable input
CS0#, CS1#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-DQM8
Data-in-mask
V
CC
Power Supply
V
CCQ
Power Supply for DQS
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Indentifi cation Flag
NC
No Connect
W3EG7262S-D3
-JD3
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2005
Rev. 3
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
DQM0
CS0#
DQS0
DQM1
DQS1
DQM2
DQS2
DQM3
DQS3
DQS8
DQM8
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
W P
A0 - A12
A0-A12 : DDR SDRAMs
RAS#
RAS# : DDR SDRAMs
CAS#
CAS# : DDR SDRAMs
CKE0
CKE0 : DDR SDRAMs
WE#
W E # : DDR SDRAMs
CKE1
CKE1 : DDR SDRAMs
BA0 - BA1
BA0-BA1 : DDR SDRAMs
CK0 / CKO#
Clock Input
SDRAMs
CK1 / CK1#
6 SDRAMs
6 SDRAMs
6 SDRAMs
CK2 / CK2#
DQM4
DQM5
CS1#
DQS4
DQS5
DQM6
DQS6
DQM7
DQS7
V
SS
V
CC
/ V
CCQ
V
R E F
V
CCSPD
DDR SDRAMs
SPD
DDR SDRAMs
DDR SDRAMs
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ23
DQ20
DQ21
DQ22
DQ16
DQ17
DQ18
DQ19
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ52
DQ53
DQ54
DQ48
DQ49
DQ50
DQ51
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
CS# DQS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS# DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ55
Notes:
1. DQ to I/O wiring is shown as recommended but may be changed.
2.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
NOTE: All resistor values are 22 ohms unless otherwise specifi ed.
W3EG7262S-D3
-JD3
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2005
Rev. 3
PRELIMINARY
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
18
W
Short Circuit Current
I
OS
50
mA
Note:
Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
ABSOLUTE MAXIMUM RATINGS
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= 2.5V 0.2V
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
2.3
2.7
V
Supply Voltage
V
CCQ
2.3
2.7
V
Reference Voltage
V
REF
1.15
1.35
V
Termination Voltage
V
TT
1.15
1.35
V
Input High Voltage
V
IH
V
REF
+ 0.15
V
CCQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
V
REF
-0.15
V
Output High Voltage
V
OH
V
TT
+ 0.76
--
V
Output Low Voltage
V
OL
--
V
TT
-0.76
V
CAPACITANCE
T
A
= 25C. f = 1MHz, V
CC
= 2.5V 0.2V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
59
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
59
pF
Input Capacitance (CKE0)
C
IN3
32
pF
Input Capacitance (CK0#,CK0)
C
IN4
56
pF
Input Capacitance (CS0#)
C
IN5
32
pF
Input Capacitance (DQM0-DQM8)
C
IN6
13
pF
Input Capacitance (BA0-BA1)
C
IN7
59
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
C
OUT
13
pF
Data input/output capacitance (CB0-CB7)
C
OUT
13
pF
W3EG7262S-D3
-JD3
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2005
Rev. 3
PRELIMINARY
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0C
T
A
70C, V
CCQ
= 2.5V 0.2V, V
CC
= 2.5V 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR266@CL=2.0
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
I
DD0
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
TBD
1845
1845
mA
Operating Current
I
DD1
One device bank; Active-Read-
Precharge Burst = 2; t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); l
OUT
= 0mA; Address
and control inputs changing once per
clock cycle.
TBD
2205
2205
mA
Precharge Power-
Down Standby
Current
I
DD2P
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
TBD
72
72
rnA
Idle Standby Current
I
DD2F
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
TBD
810
810
mA
Active Power-Down
Standby Current
I
DD3P
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
TBD
450
450
mA
Active Standby
Current
I
DD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
TBD
900
900
mA
Operating Current
I
DD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
TBD
2250
2250
mA
Operating Current
I
DD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
TBD
2115
2115
rnA
Auto Refresh
Current
I
DD5
t
RC
= t
RC
(MIN)
TBD
3015
3015
mA
Self Refresh Current
I
DD6
CKE
0.2V
TBD
72
72
mA
Operating Current
I
DD7A
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and
control inputs change only during
Active Read or Write commands.
TBD
4050
4050
mA
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