W3H32M72E-XSBX
PRELIMINARY*
1
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White Electronic Designs
February 2006
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667*, 533, 400
Package:
208 Plastic Ball Grid Array (PBGA), 18 x 20mm
1.0mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data output drive strength
Single 1.8V 0.1V supply
Programmable CAS latency: 3, 4, 5, or 6
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial,
Industrial
and
Military
Temperature
Rang es
Organized as 32M x 72
Weight: W3H32M72E-XSBX - 2.5 grams typical
BENEFITS
65% SPACE SAVINGS vs. FPBGA
Re
duced part count
54% I/O reduction vs FPBGA
Re
duced trace lengths for low er par a sit ic
ca pac i tance
Suit
able for hi-re li abil i ty ap pli ca tions
Upgradable to 64M x 72 den si ty (con tact fac to ry for
information)
* This product is under development, is not qualifi ed or characterized and is subject
to change without notice.
Area
5 x 209mm
2
= 1,045mm
2
360mm
2
65%
5 x 90 balls = 450 balls
208 Balls
54%
S
A
V
I
N
G
S
I/O
Count
Actual Size
W3H32M72E-XSBX
CSP Approach (mm)
90
FBGA
11.0
19.0
20
18
90
FBGA
11.0
90
FBGA
11.0
90
FBGA
11.0
90
FBGA
11.0
FIGURE 1 DENSITY COMPARISONS
White Electronic Designs
W3H32M72E-XSBX
W3H32M72E-XSBX
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White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DQ16
DQ31
DQ0
DQ15
WE#
CS#
RAS# CAS# CKE
DQ32
DQ47
DQ0
DQ15
WE#
CS#
RAS# CAS# CKE
DQ48
DQ63
DQ0
DQ15
CKE
DQ64
DQ0
CKE
A0-12
BA0-1
U1
RAS#
WE#
CAS#
CKE
CS#
U0
U2
U3
A0-12
BA0-1
ODT
A0-12
BA0-1
ODT
A0-12
BA0-1
ODT
A0-12
BA0-1
ODT
A0-12
BA0-1
CK4#
CK#
LDM4
LDM
LDQS4
LDQS#
UDQS4
LDQS4#
UDQS4#
UDQS#
LDQS
UDQS
ODT
CK4
CK
ODT
U4
CK3#
CK#
LDM3
LDM
UDM3
UDM
LDQS3
LDQS#
UDQS3
LDQS3#
UDQS3#
UDQS#
LDQS
UDQS
CK3
CK
CK2#
CK#
LDM2
LDM
UDM2
UDM
LDQS2
LDQS#
UDQS2
LDQS2#
UDQS2#
UDQS#
LDQS
UDQS
CK2
CK
CK1#
CK#
LDM1
LDM
UDM1
UDM
LDQS1
LDQS#
UDQS1
LDQS1#
UDQS1#
UDQS#
LDQS
UDQS
CK1
CK
CK0#
CK#
LDM0
LDM
UDM0
UDM
LDQS0
LDQS#
UDQS0
LDQS0#
UDQS0#
UDQS#
LDQS
UDQS
CK0
CK
DQ0
DQ15
DQ0
DQ15
WE#
CS#
RAS# CAS# CKE
WE#
CS#
RAS# CAS#
DQ71
DQ8
WE#
CS#
RAS# CAS#
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
Note: UDQS4 and UDQS4# require a 10 K pull up resistor.
W3H32M72E-XSBX
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White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TOP VIEW
FIGURE 3 PIN CONFIGURATION
1 2 3 4 5 6 7 8 9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CC
V
SS
DQ35
DQ52
LDM3
DQ38
UMD3
V
CC
V
SS
V
CC
UDQS1#
DQ13
LDQS1#
DQ0
CK0
V
SS
V
CC
V
SS
V
CC
V
SS
NC
DQ51
DQ36
LDM2
DQ54
DQ44
A6
A0
A2
UDQS1
DQ29
LDQS0#
DQ16
CK0#
CK1#
V
SS
V
CC
V
SS
NC
NC
NC
DQ33
DQ49
DQ60
DQ41
A10
A11
A4
UDQS0
DQ8
DQ10
LDQS1
DQ5
CK1
CK4#
V
SS
V
CC
NC
NC
NC
NC
DQ43
DQ57
DQ46
A9
V
CC
A8
DQ15
DQ24
DQ26
LDQS0
DQ21
DQ2
CK4
V
CC
V
CC
NC
NC
NC
DNU**
DQ59
UMD2
DQ62
V
CC
V
SS
V
CC
UDQS0#
DQ31
DQ23
DQ7
DQ18
RAS#
CS#
V
CC
V
CC
NC
NC
DQ50
DQ39
DQ55
DQ63
UDQS2#
V
CC
V
SS
V
CC
DQ30
UDM0
DQ27
UDQS4
DQ71
DQ64
DQ69
Vcc
V
CC
V
SS
CK3#
CK2#
DQ48
LDQS2#
DQ61
UDQS3
DNU*
BA1
A7
DQ12
DQ22
LDM0
DQ4
DQ19
DQ68
V
SS
V
CC
V
CC
NC
DQ34
DQ53
LDQS2
DQ58
DQ56
DQ47
A3
V
CC
BA0
DQ14
DQ25
DQ11
UDQS4#
CKE
DQ70
LDM4
V
CC
V
SS
NC
CK3
DQ37
LDQS3
DQ42
DQ40
UDQS2
A12
A1
A5
DQ9
DQ28
DQ17
DQ1
WE#
DQ65
DQ67
V
SS
V
SS
NC
NC
NC
DNU
DNU
V
SS
V
CC
V
SS
V
REF
V
SS
V
CC
V
SS
ODT
LDQS4#
LDQS4
CAS#
DQ66
V
SS
V
SS
V
CC
V
SS
CK2
DQ32
LDQS3#
DQ45
UDQS3#
V
CC
V
SS
V
CC
UMD1
DQ6
LDM1
DQ20
DQ3
V
SS
V
CC
V
SS
* Pin J10 is reserved for signal A13 on 128Mx72 and higher densities.
** Pin E5 is reserved for signal BA2 on 64Mx72 and higher densities.
Note:
UDQS4 and UDQS4# require a 10 K pull up resistor.
W3H32M72E-XSBX
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TABLE 1 BALL DESCRIPTIONS
Symbol
Type
Description
ODT
Input
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each of the following balls: DQ0DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and
UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the
crossings of CK and CK#.
CKE
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the
DDR2 SDRAM. The specifi c circuitry that is enabled/disabled is dependent on the DDR2 SDRAM confi guration
and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks
idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down
exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding
CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.
CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V
CC
is applied during fi rst power-up. After
V
REF
has become stable during the power on and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF-REFRESH operation, V
REF
must be maintained.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands
are masked when CS# is registered HIGH.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, WE# (along with CS#) defi ne the command being entered.
LDM, UDM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled
HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM
loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0DQ7 and UDM is DM for
upper byte DQ8DQ15, of each of U0-U4
BA0BA1
Input
Bank address inputs: BA0BA1 defi ne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is
being applied. BA0BA1 defi ne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the
LOAD MODE command.
Continued on next page
W3H32M72E-XSBX
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TABLE 1 BALL DESCRIPTIONS (continued)
A0-A12
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA1BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
DQ0-71
I/O
Data input/output: Bidirectional data bus
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
V
CC
Supply
Power Supply: 1.8V 0.1V
V
CCQ
Supply
DQ Power supply: 1.8V 0.1V. Isolated on the device for improved noise immunity
V
REF
Supply
SSTL_18 reference voltage.
V
SS
Supply
Ground
NC
-
No connect: These balls should be left unconnected.
DNU
-
Future use; Row address bits A14 and A15 are reserved for 8Gb and 16Gb densities. BA2 is reserved for 4Gb
device.
W3H32M72E-XSBX
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DESCRIPTION
The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic
random-access memory containing 2,147,483,648 bits.
Each of the fi ve ships in the MCP are internally confi gured
as 4-bank DRAM. The block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
The 2Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O balls. A single read or write
access for the 2Gb DDR2 SDRAM effectively consists of
a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during
WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. There are strobes,
one for the lower byte (LDQS, LDQS#) and one for the
upper byte (UDQS, UDQS#).
The 2Gb DDR2 SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another write.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the
burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving
power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_18. All full drive-strength outputs are SSTL_18-
compatible.
GENERAL NOTES
The functionality and the timing specifi cations
discussed in this data sheet are for the DLL-
enabled mode of operation.
Throughout the data sheet, the various fi gures and
text refer to DQs as "DQ." The DQ term is to be
interpreted as any and all DQ collectively, unless
specifi cally stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0DQ7), DM refers to
LDM and DQS refers to LDQS. For the upper byte
(DQ8DQ15), DM refers to UDM and DQS refers to
UDQS. Note that the there is no upper byte for U4
and therefore no UDM4.
Complete functionality is described throughout
the document and any page or diagram may have
been simplifi ed to convey a topic and may not be
inclusive of all requirements.
Any specifi c requirement takes precedence over a
general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefi ned manner. Operational procedures other
than those specifi ed may result in undefi ned operation.
The following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
1.
Applying power; if CKE is maintained below 0.2 x
V
CCQ
, outputs remain disabled. To guarantee R
TT
(ODT resistance) is off, V
REF
must be valid and a
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White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
low level must be applied to the ODT ball (all other
inputs may be undefi ned, I/Os and outputs must be
less than V
CCQ
during voltage ramp time to avoid
DDR2 SDRAM device latch-up). At least one of the
following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply
defi ned as V
CC
, V
CCQ
, V
REF
, and V
TT
are between
their minimum and maximum values as stated in
Table20):
A.
(single power source) The V
CC
voltage ramp
from 300mV to V
CC
(MIN) must take no longer
than 200ms; during the V
CC
voltage ramp, |V
CC
-
V
CCQ
| 0.3V. Once supply voltage ramping
is complete (when V
CCQ
crosses V
CC
(MIN)),
Table20 specifi cations apply.
V
CC
, V
CCQ
are driven from a single power
converter output
V
TT
is limited to 0.95V MAX
V
REF
tracks V
CCQ/2
; V
REF
must be within
0.3V with respect to V
CCQ/2
during supply
ramp time
V
CCQ
V
REF
at all times
B.
(multiple power sources) V
CC
V
CCQ
must be
maintained during supply voltage ramping, for
both AC and DC levels, until supply voltage
ramping completes (V
CCQ
crosses V
CC
[MIN]).
Once supply voltage ramping is complete,
Table20 specifi cations apply.
Apply V
CC
before or at the same time as
V
CCQ
; V
CC
voltage ramp time must be
200ms from when V
CC
ramps from 300mV to
V
CC
(MIN)
Apply V
CCQ
before or at the same time as
V
TT
; the V
CCQ
voltage ramp time from when
V
CC
(MIN) is achieved to when V
CCQ
(MIN)
is achieved must be 500ms; while V
CC
is
ramping, current can be supplied from V
CC
through the device to V
CCQ
V
REF
must track V
CCQ/2,
V
REF
must be within
0.3V with respect to V
CCQ/2
during supply
ramp time; V
CCQ
V
REF
must be met at all
times
Apply V
TT
; The V
TT
voltage ramp time from
when V
CCQ
(MIN) is achieved to when V
TT
(MIN) is achieved must be no greater than
500ms
2.
For a minimum of 200s after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands
and take CKE HIGH.
3.
Wait a minimum of 400ns, then issue a
PRECHARGE ALL command.
4.
Issue an LOAD MODE command to the EMR(2).
(To issue an EMR(2) command, provide LOW to
BA0, provide HIGH to BA1.)
5.
Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0
and BA1.)
6.
Issue an LOAD MODE command to the EMR to
enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0, provide HIGH to BA0.
Bits E7, E8, and E9 can be set to "0" or "1"; Micron
recommends setting them to "0."
7.
Issue a LOAD MODE command for DLL RESET.
200 cycles of clock input is required to lock the
DLL. (To issue a DLL RESET, provide HIGH to A8
and provide LOW to BA1, and BA0.) CKE must be
HIGH the entire time.
8.
Issue PRECHARGE ALL command.
9.
Issue two or more REFRESH commands, followed
by a dummy WRITE.
W3H32M72E-XSBX
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
V
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FIGURE 4 POWER-UP AND INITIALIZATION
Notes appear on page 9
W3H32M72E-XSBX
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
NOTES:
1.
Applying power; if CKE is maintained below 0.2 x V
CCQ
, outputs remain disabled.
To guarantee R
TT
(ODT resistance) is off, VREF must be valid and a low level must
be applied to the ODT ball (all other inputs may be undefi ned, I/Os and outputs
must be less than V
CCQ
during voltage ramp time to avoid DDR2 SDRAM device
latch-up). At least one of the following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply defi ned as V
CC
, V
CCQ
,V
REF
, and
V
TT
are between their minimum and maximum values as stated in DC Operating
Conditions table):
A. (single power source) The V
CC
voltage ramp from 300mV to V
CC
(MIN) must
take no longer than 200ms; during the V
CC
voltage ramp, |V
CC
- V
CCQ
| 0.3V.
Once supply voltage ramping is complete (when V
CCQ
crosses V
CC
(MIN), DC
Operating Conditions table specifi cations apply.
V
CC
, V
CCQ
are driven from a single power converter output
V
TT
is limited to 0.95V MAX
V
REF
tracks V
CCQ/2
; V
REF
must be within 0.3V with respect to V
CCQ/2
during
supply ramp time.
V
CCQ
V
REF
at all times
B. (multiple power sources) V
CC
V
CCQ
must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes
(V
CCQ
crosses V
CC
[MIN]). Once supply voltage ramping is complete, DC
Operating Conditions table specifi cations apply.
Apply V
CC
before or at the same time as V
CCQ
; V
CC
voltage ramp time must
be 200ms from when V
CC
ramps from 300mV to V
CC
(MIN)
Apply V
CCQ
before or at the same time as V
TT
; the V
CCQ
voltage ramp time
from when V
CC
(MIN) is achieved to when V
CCQ
(MIN) is achieved must be
500ms; while V
CC
is ramping, current can be supplied from V
CC
through the
device to V
CCQ
V
REF
must track V
CCQ/2
, V
REF
must be within 0.3V with respect to V
CCQ/2
during supply ramp time; V
CCQ
V
REF
must be met at all times
Apply V
TT
; The V
TT
voltage ramp time from when V
CCQ
(MIN) is achieved to
when
VTT
(MIN) is achieved must be no greater than 500ms
2.
For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or
DESELECT commands and take CKE HIGH.
3.
Wait a minimum of 400ns, then issue a PRECHARGE ALL command/
4.
Issue an LOAD MODE command to the EMR(2). (To issue an EMR(2) command,
provide LOW to BA0, provide HIGH to BA1.)
5.
Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command,
provide HIGH to BA0 and BA1.)
6.
Issue an LOAD MODE command to the EMR to enable DLL. To issue a DLL
ENABLE command, provide LOW to BA1 and A0, provide HIGH to BA0. Bits E7,
E8, and E9 can be set to "0" or "1"; Micron recommends setting them to "0."
7.
Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is
required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire time.
8.
Issue PRECHARGE ALL command.
9.
Issue two or more REFRESH commands, followed by a dummy WRITE.
10. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,
to program operating parameters without resetting the DLL).
11. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits
E7, E8, and E9 to "1," and then setting all other desired parameters.
12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,
E8, and E9 to "0," and then setting all other desired parameters.
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,
to program operating parameters without resetting the DLL).
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits
E7,E8, and E9 to "1," and then setting all other desired parameters.
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,
E8, and E9 to "0," and then setting all other desired parameters.
The DDR2 SDRAM is now initialized and ready for normal operation 200 clocks after
DLL RESET (in step 7).
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White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
MODE REGISTER (MR)
The mode register is used to defi ne the specifi c mode of
operation of the DDR2 SDRAM. This defi nition includes
the selection of a burst length, burst type, CL, operating
mode, DLL RESET, write recovery, and power-down mode,
as shown in Figure 5. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command.
If the user chooses to modify only a subset of the MR
variables, all variables (M0M14) must be programmed
when the command is issued.
The mode register is programmed via the LM command
(bits BA1BA0 = 0, 0) and other bits (M12M0) will retain
the stored information until it is programmed again or
the device loses power (except for bit M8, which is self-
clearing). Reprogramming the mode register will not alter
the contents of the memory array, provided it is performed
correctly.
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. The controller must wait the specifi ed
time
t
MRD before initiating any subsequent operations
such as an ACTIVE command. Violating either of these
requirements will result in unspecifi ed operation.
BURST LENGTH
Burst length is defi ned by bits M0M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are
burst-oriented, with the burst length being programmable
to either four or eight. The burst length dete rmines
the maximum number of column locations that can be
accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A2Ai when BL = 4 and by A3Ai when BL = 8 (where
Ai is the most signifi cant column address bit for a given
confi guration). The remaining (least signifi cant) address
bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both READ
and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. The burst type is selected
via bit M3, as shown in Figure 5. The ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address
ordering is nibble-based.
Burst Length
CAS# Latency BT
PD
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
0
1
14
Burst Length
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
0
1
Burst Type
Sequential
Interleaved
M3
CAS Laten cy (CL)
Reserved
Reserved
Reserved
3
4
5
6
Reserved
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M 6
0
0
0
0
1
1
1
1
0
1
Mo de
Normal
Test
M7
15
DLL TM
0
1
DLL Reset
No
Yes
M 8
WRITE RECOVERY
Reserved
2
3
4
5
6
Reserved
Reserved
M9
0
1
0
1
0
1
0
1
M10
0
0
1
1
0
0
1
1
M11
0
0
0
0
1
1
1
1
WR
A13
MR
0
1
0
1
Mo de Register Definition
Mode Register (MR)
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
M15
0
0
1
1
0
1
PD mode
Fast Exit
(Normal)
Slow Exit
(Low Power)
M12
M14
FIGURE 5 MODE REGISTER (MR) DEFINITION
Note: 1. Not used on this part
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White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TABLE 2 BURST DEFINITION
NOTES:
1.
For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2.
For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3.
For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
Burst
Length
Starting Column
Address
Order of Accesses With in a Burst
Type = Sequential
Type = In ter leaved
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
OPERATING MODE
The normal operating mode is selected by issuing a
command with bit M7 set to "0," and all other bits set to
the desired values, as shown in Figure 5. When bit M7 is
"1," no other bits of the mode register are programmed.
Programming bit M7 to "1" places the DDR2 SDRAM into a
test mode that is only used by the manufacturer and should
not be used. No operation or functionality is guaranteed
if M7 bit is `1.'
DLL RESET
DLL RESET is defi ned by bit M8, as shown in Figure 5.
Programming bit M8 to "1" will activate the DLL RESET
function. Bit M8 is self-clearing, meaning it returns back
to a value of "0" after the DLL RESET function has been
issued.
Anytime the DLL RESET function is used, 200 clock cycles
must occur before a READ command can be issued to
allow time for the internal clock to be synchronized with
the external clock. Failing to wait for synchronization
to occur may result in a violation of the
t
AC or
t
DQSCK
parameters.
WRITE RECOVERY
Write recovery (WR) time is defi ned by bits M9M11, as
shown in Figure 5. The WR register is used by the DDR2
SDRAM during WRITE with auto precharge operation.
During WRITE with auto precharge operation, the DDR2
SDRAM delays the internal auto precharge operation by
WR clocks (programmed in bits M9M11) from the last
data burst.
WR values of 2, 3, 4, 5, or 6 clocks may be used for
programming bits M9M11. The user is required to
program the value of WR, which is calculated by dividing
t
WR (in ns) by
t
CK (in ns) and rounding up a non integer
value to the next integer; WR [cycles] =
t
WR [ns] /
t
CK [ns].
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
POWER-DOWN MODE
Active power-down (PD) mode is defi ned by bit M12,
as shown in Figure 5. PD mode allows the user to
determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does
not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode or "fast-exit"
active PD mode is enabled. The
t
XARD parameter is used
for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode or "slow-
exit" active PD mode is enabled. The
t
XARD parameter is
used for slow-exit active PD exit timing. The DLL can be
enabled, but "frozen" during active PD mode since the exit-
to-READ command timing is relaxed. The power difference
expected between PD normal and PD low-power mode is
defi ned in the I
CC
table.
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White Electronic Designs
February 2006
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PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
CAS LATENCY (CL)
The CAS latency (CL) is defi ned by bits M4M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of
the fi rst bit of output data. The CL can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to
t
RCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
Examples of CL = 3 and CL = 4 are shown in Figure 6;
both assume AL = 0. If a READ command is registered
at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
D
OUT
n + 3
D
OUT
n + 2
D
OUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal
t AC, tDQSCK, and tDQSQ
T0
T1
T2
DON'T CARE
TRANSITIONING DATA
NOP
NOP
NOP
D
OUT
n
T3
T4
T5
NOP
NOP
T6
NOP
D
OUT
n + 3
D
OUT
n + 2
D
OUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
NOP
NOP
D
OUT
n
T3
T4
T5
NOP
NOP
T6
NOP
FIGURE 6 CAS LATENCY (CL)
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White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specifi ed time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecifi ed operation.
FIGURE 7 EXTENDED MODE REGISTER DEFINITION
DLL
Posted CAS# Rtt
out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
0
2
14
Poste d CAS# Add itive Laten cy (AL)
0
1
2
3
4
Reserved
Reserved
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
0
1
1
0
0
1
1
E5
0
0
0
0
1
1
1
1
0
1
DLL Enable
Enable (Normal)
Disable (Test/Debug)
E0
15
0
1
RDQS Enable
No
Yes
E11
OCD Program
A13
ODS
Rtt
DQS#
0
1
DQS# Enable
Enable
Disable
E10
RDQS
Rtt (nominal)
Rtt Disabled
75
150
50
E2
0
1
0
1
E6
0
0
1
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mo de Register Set
Mode Register Set (MR S)
Extended Mode Register (EMR S)
Extended Mode Register (EMR S2)
Extended Mode Register (EMR S3)
E15
0
0
1
1
E14
MRS
OCD Operation
OCD Not Supported
1
Reserved
Reserved
Reserved
OCD default state
1
E7
0
1
0
0
1
E8
0
0
1
0
1
E9
0
0
0
1
1
0
1
Output Drive Strength
E1
Full Strength (18 target)
Reduced Strength (40 target)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is fi nished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
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White Electronic Designs
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PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit
E0 during the LM command, as shown in Figure 7. The
DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning
to normal operation after having disabled the DLL for the
purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using an
LM command.
The DLL is automatically disabled when entering SELF
REFRESH operation and is automatically re-enabled and
reset upon exit of SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200
clock cycles must occur before a READ command can be
issued, to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization
to occur may result in a violation of the
t
AC or
t
DQSCK
parameters.
OUTPUT DRIVE STRENGTH
The output drive strength is defi ned by bit E1, as shown
in Figure 7. The normal drive strength for all outputs are
specifi ed to be SSTL_18. Programming bit E1 = 0 selects
normal (full strength) drive strength for all outputs. Selecting
a reduced drive strength option (E1 = 1) will reduce all
outputs to approximately 60 percent of the SSTL_18 drive
strength. This option is intended for the support of lighter
load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0,
DQS# is the complement of the differential data strobe pair
DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single ended mode and the DQS# ball is disabled. When
disabled, DQS# should be left fl oating. This function is also
used to enable/disable RDQS#. If RDQS is enabled (E11
= 1) and DQS# is enabled (E10 = 0), then both DQS# and
RDQS# will be enabled.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defi ned by bit E12, as
shown in Figure 7. When enabled (E12 = 0), all outputs
(DQs, DQS, DQS#, RDQS, RDQS#) function normally.
When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs,
DQS, DQS#, RDQS, RDQS#) are disabled, thus removing
output buffer current. The output disable feature is intended
to be used during I
CC
characterization of read current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, R
TT
(EFF), is defi ned by bits
E2 and E6 of the EMR, as shown in Figure 7. The ODT
feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller
to independently turn on/off ODT for any or all devices.
R
TT
effective resistance values of 50 ,75, and 150
are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/
LDM signals. Bits (E6, E2) determine what ODT resistance
is enabled by turning on/off "sw1," "sw2," or "sw3." The
ODT effective resistance value is elected by enabling
switch "sw1," which enables all R1 values that are 150
each, enabling an effective resistance of 75 (R
TT2
(EFF)
= R2/2). Similarly, if "sw2" is enabled, all R2 values that
are 300 each, enable an effective ODT resistance of
150 (R
TT2
(EFF) = R2/2). Switch "sw3" enables R1 values
of 100 enabling effective resistance of 50 Reserved
states should not be used, as unknown operation or
incompatibility with future versions may result.
The ODT control ball is used to determine when R
TT
(EFF)
is turned on and off, assuming ODT has been enabled via
bits E2 and E6 of the EMR. The ODT feature and ODT
input ball are only used during active, active power-down
(both fast-exit and slow-exit modes), and precharge power-
down modes of operation. ODT must be turned off prior to
entering self refresh. During power-up and initialization of
the DDR2 SDRAM, ODT should be disabled until issuing
the EMR command to enable the ODT feature, at which
point the ODT ball will determine the R
TT
(EFF) value.
Any time the EMR enables the ODT function, ODT may
not be driven HIGH until eight clocks after the EMR has
been enabled. See "ODT Timing" section for ODT timing
diagrams.
W3H32M72E-XSBX
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White Electronic Designs
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POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3E5 defi ne the value
of AL, as shown in Figure 7. Bits E3E5 allow the user
to program the DDR2 SDRAM with an inverse AL of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
WRITE command to be issued prior to
t
RCD (MIN) with
the requirement that AL
t
RCD (MIN). A typical application
using this feature would set AL =
t
RCD (MIN) - 1x
t
CK. The
READ or WRITE command is held for the time of the AL
before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL+CL.
Write latency (WL) is equal to RL minus one clock; WL =
AL + CL - 1 x
t
CK.
A9
A7 A 6 A5 A4 A3
A8
A2
A1 A0
Extended Mo de
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
0
1
14
15
A13
0
1
0
1
Mode Register Definition
Mo de Register (MR)
Extended Mo de Register (EMR)
Extended Mo de Register (EMR2)
Extended Mo de Register (EMR3)
M 15
0
0
1
1
M 14
EMR2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
High Temperature Self Refresh rate enable
Commer cial-Temperature default
Industrial-Temperature option;
use if T
C
exceeds 85C
E7
0
1
FIGURE 8 EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
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EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions
beyond those controlled by the mode register. Currently
all bits in EMR2 are reserved, as shown in Figure 8. The
EMR2 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
EMR2 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specifi ed time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecifi ed operation.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions
beyond those controlled by the mode register. Currently,
all bits in EMR3 are reserved, as shown in Figure 9.
The EMR3 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
EMR3 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specifi ed time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecifi ed operation.
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2
SDRAM available commands, including CKE power-down
modes, and bank-to-bank commands.
FIGURE 9 EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
A9
A7 A 6 A5 A4 A3
A8
A2
A1 A0
Extended Mo de
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
14
15
A13
0
1
0
1
Mode Register Definition
Mo de Register (MR)
Extended Mo de Register (EMR)
Extended Mo de Register (EMR2)
Extended Mo de Register (EMR3)
M 15
0
0
1
1
M 14
EMR3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
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TABLE 3 TRUTH TABLE - DDR2 COMMANDS
Notes appear on page 9
Function
CKE
CS#
RAS#
CAS#
WE#
BA1
BA0
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
H
L
L
L
L
BA
OP Code
2
REFRESH
H
H
L
L
L
H
X
X
X
X
SELF-REFRESH Entry
H
L
L
L
L
H
X
X
X
X
SELF-REFRESH Exit
L
H
H
X
X
X
X
X
X
X
7
L
H
H
H
Single bank precharge
H
H
L
L
H
L
X
X
L
X
2
All banks PRECHARGE
H
H
L
L
H
L
X
X
H
X
Bank activate
H
H
L
L
H
L
BA
Row Address
WRITE
H
H
L
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
H
H
L
H
L
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
H
L
H
L
H
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
H
L
H
L
H
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
H
H
X
X
X
X
Device DESELECT
H
X
H
X
X
X
X
X
X
X
POWER-DOWN entry
H
L
H
X
X
X
X
X
X
X
4
L
H
H
H
POWER-DOWN exit
L
H
H
X
X
X
X
X
X
X
4
L
H
H
H
Note: 1. All DDR2 SDRAM commands are defi ned by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0BA12 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See "On-Die Termination (ODT)" for details.
6. "X" means "H or L" (but a defi ned logic level).
7. Self refresh exit is asynchronous.
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DESELECT
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR2 SDRAM.
The DDR2 SDRAM is effectively deselected. Operations
already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct
the selected DDR2 SDRAM to perform a NOP (CS# is
LOW; RAS#, CAS#, and WE are HIGH). This prevents
unwanted commands from being registered during idle
or wait states. Operations already in progress are not
affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA1BA0, and
A12A0. BA1BA0 determine which mode register will
be programmed. See "Mode Register (MR)". The LM
command can only be issued when all banks are idle, and
a subsequent execute able command cannot be issued
until
t
MRD is met.
BANK/ROW ACTIVATION
ACTIVE COMMAND
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA1BA0 inputs selects the bank, and the
address provided on inputs A12A0 selects the row.
This row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
ACTIVE OPERATION
Before any READ or WRITE commands can be issued to
a bank within the DDR2 SDRAM, a row in that bank must
be opened (activated), even when additive latency is used.
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ
or WRITE command may be issued to that row, subject to
the
t
RCD specifi cation.
t
RCD (MIN) should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. The same procedure is used to convert other
specifi cation limits from time units to clock cycles. For
example, a
t
RCD (MIN) specifi cation of 20ns with a 266
MHz clock (
t
CK = 3.75ns) results in 5.3 clocks, rounded
up to 6.
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defi ned by
t
RC
A subsequent ACTIVE command to another bank can be
issued while the fi rst bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defi ned by
t
RRD
FIGURE 10 ACTIVE COMMAND
DON'T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Row
Bank
ADDRESS
BANK ADDRESS
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READ COMMAND
The READ command is used to initiate a burst read access
to an active row. The value on the BA1BA0 inputs selects
the bank, and the address provided on inputs A0i (where
i = A9) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
READ OPERATION
READ bursts are initiated with a READ command. The
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RL) clocks later. RL is defi ned as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. The initial LOW state on DQS and HIGH state
on DQS# is known as the read preamble (
t
RPRE). The
LOW state on DQS and HIGH state on DQS# coincident
with the last data-out element is known as the read
postamble (
t
RPST).
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous fl ow of data. The fi rst data element from the
new burst follows the last element of a completed burst.
The new READ command should be issued x cycles after
the fi rst READ command, where x equals BL / 2 cycles.
FIGURE 11 READ COMMAND
DON'T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Col
Bank
ADDRESS
BANK ADDRESS
AUTO PRECHARGE
ENABLE
DISABLE
A10
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WRITE COMMAND
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA1BA0 inputs
selects the bank, and the address provided on inputs A09
selects the starting column location. The value on input
A10 determines whether or not auto precharge is used.
If auto precharge is selected, the row being accessed
will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered
LOW, the corresponding data will be written to memory; if
the DM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed
to that byte/column location.
WRITE OPERATION
WRITE bursts are initiated with a WRITE command, as
shown in Figure 12. DDR2 SDRAM uses WL equal to RL
minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)].
The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
During WRITE bursts, the fi rst valid data-in element will
be registered on the fi rst rising edge of DQS following the
WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state
on DQS between the WRITE command and the fi rst rising
edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the
write postamble.
The time between the WRITE command and the fi rst rising
DQS edge is WL
t
DQSS. Subsequent DQS positive rising
edges are timed, relative to the associated clock edge, as
t
DQSS.
t
DQSS is specifi ed with a relatively wide range
(25 percent of one clock cycle). All of the WRITE diagrams
show the nominal case, and where the two extreme cases
(
t
DQSS [MIN] and
t
DQSS [MAX]) might not be intuitive,
they have also been included. Upon completion of a burst,
assuming no other commands have been initiated, the
DQ will remain High-Z and any additional input data will
be ignored.
Data for any WRITE burst may be concatenated with a
subsequent WRITE command to provide continuous fl ow
of input data. The fi rst data element from the new burst is
applied after the last element of a completed burst. The
new WRITE command should be issued x cycles after the
fi rst WRITE command, where x equals BL/2.
DDR2 SDRAM supports concurrent auto precharge
options, as shown in Table 4.
DDR2 SDRAM does not allow interrupting or truncating
any WRITE burst using BL = 4 operation. Once the BL
= 4 WRITE command is registered, it must be allowed
to complete the entire WRITE burst cycle. However,
a WRITE (with auto precharge disabled) using BL = 8
operation might be interrupted and truncated ONLY by
another WRITE burst as long as the interruption occurs
on a 4-bit boundary, due to the 4n prefetch architecture of
DDR2 SDRAM. WRITE burst BL = 8 operations may not
to be interrupted or truncated with any command except
another WRITE command.
Data for any WRITE burst may be followed by a
subsequent READ command. The number of clock cycles
required to meet
t
WTR is either 2 or
t
WTR/
t
CK, whichever
is greater. Data for any WRITE burst may be followed by a
subsequent PRECHARGE command.
t
WT starts at the end
of the data burst, regardless of the data mask condition.
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FIGURE 12 WRITE COMMAND
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BANK ADDRESS
HIGH
EN AP
DIS AP
BA
CK
CK#
DON'T CARE
ADDRESS
Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and
DIS AP = disable auto precharge.
TABLE 4 WRITE USING CONCURRENT AUTO PRECHARGE
From Command (Bank n)
To Command (Bank m)
Minimum Delay (With Concurrent
Auto Precharge)
Units
WRITE with Auto Precharge
READ OR READ w/AP
(CL-1) + (BL/2) +
t
WTR
t
CK
WRITE or WRITE w/AP
(BL/2)
t
CK
PRECHARGE or ACTIVE
1
t
CK
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PRECHARGE COMMAND
The PRECHARGE command, illustrated in Figure 13, is
used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available
for a subsequent row activation a specifi ed time (
t
RP
)
after the PRECHARGE command is issued, except in
the case of concurrent auto precharge, where a READ or
WRITE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters.
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE
command is allowed if there is no open row in that bank
(idle state) or if the previously open row is already in the
process of precharging. However, the precharge period
will be determined by the last PRECHARGE command
issued to the bank.
PRECHARGE OPERATION
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA1BA0 select the bank. Otherwise
BA1BA0 are treated as "Don't Care."
When all banks are to be precharged, inputs BA1BA0
are treated as "Don't Care." Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that
bank.
t
RPA timing applies when the PRECHARGE (ALL)
command is issued, regardless of the number of banks
already open or closed. If a single-bank PRECHARGE
command is issued,
t
RP timing applies.
SELF REFRESH COMMAND
The SELF REFRESH command can be used to retain
data in the DDR2 SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR2 SDRAM retains data without external clocking. All
power supply inputs (including V
REF
) must be maintained
at valid levels upon entry/exit and during SELF REFRESH
operation.
The SELF REFRESH command is initiated like a
REFRESH command except CKE is LOW. The DLL is
automatically disabled upon entering self refresh and is
automatically enabled upon exiting self refresh (200 clock
cycles must then occur before a READ command can be
CS#
WE#
CAS#
RAS#
CKE
A10
BA0, BA1
HIGH
ALL BANKS
ONE BANK
BA
ADDRESS
CK
CK#
DON'T CARE
FIGURE 13 PRECHARGE COMMAND
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
issued). The differential clock should remain stable and
meet
t
CKE specifi cations at least 1 x
t
CK after entering
self refresh mode. All command and address input signals
except CKE are "Don't Care" during self refresh.
The procedure for exiting self refresh requires a sequence
of commands. First, the differential clock must be stable
and meet
t
CK specifi cations at least 1 x
t
CK prior to CKE
going back HIGH. Once CKE is HIGH (
t
CLE(MIN) has
been satisfi ed with four clock registrations), the DDR2
SDRAM must have NOP or DESELECT commands issued
for
t
XSNR because time is required for the completion of
any internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply
NOP or DESELECT commands for 200 clock cycles before
applying any other command.
Note: Self refresh not available at military temperature..
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DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
V
CC
1 .7
1 .8
1 .9
V
1
I/O Supply voltage
V
CCQ
1 .7
1 .8
1 .9
V
4
I/O Reference voltage
V
REF
0.49 x V
CCQ
0.50 x V
CCQ
0.51 x V
CCQ
V
2
I/O Termination voltage
V
TT
V
REF
-0.04
V
REF
V
REF
+ 0.04
V
3
Notes:
1. V
CC
V
CCQ
must track each other. V
CCQ
must be less than or equal to V
CC
.
2. V
REF
is expected to equal V
CCQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not exceed 1 percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed 2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
4. V
CCQ
tracks with V
CC
track with V
CC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
MIN
MAX
U nit
V
CC
Voltage on V
CC
pin relative to V
SS
-1.0
2.3
V
V
CCQ
Voltage on V
CCQ
pin relative to V
SS
-0.5
2.3
V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
-0.5
2.3
V
T
STG
Storage temperature
-55
125
C
T
CASE
Device operating temperature
-55
125
C
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V<V
IN
<0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
-25
25
A
CK, CK#
-10
10
A
DM
-5
5
A
I
OZ
Output leakage current;
0V<V
OUT
<V
CCQ
; DQs and ODT are disable
DQ, DQS, DQS#
-5
5
A
I
VREF
V
REF
leakage current; V
REF
= Valid V
REF
level
-18
18
A
INPUT/OUTPUT CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= V
CCQ
= 1.8V
Parameter
Symbol
Max
Unit
Input capacitance (A0 - A12, BA0 - BA1 ,CS#, RAS#,CAS#,WE#, CKE, ODT)
C
IN1
TBD
pF
Input capacitance CK, CK#
C
IN2
TBD
pF
Input capacitance DM, DQS, DQS#
C
IN3
TBD
pF
Input capacitance DQ0 - 71
C
OUT
TBD
pF
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INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
V
IH
(DC)
V
REF
+ 0.1 25
V
CCQ
+ 0.300
V
Input Low (Logic 0) Voltage
V
IL
(DC)
-0.300
V
REF
- 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
V
IH
(AC)
V
REF
+ 0.250
--
V
AC Input High (Logic 1) Voltage DDR2-667
V
IH
(AC)
V
REF
+ 0.200
--
V
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
V
IL
(AC)
--
V
REF
- 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667
V
IL
(AC)
--
V
REF
- 0.200
V
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DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
VCC = 1.8V 0.1V; -55C T
A
125C
Symbol
Proposed Conditions
533 CL4
400 CL3
Units
I
CC0
Operating one bank active-precharge current;
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
550
550
mA
I
CC1
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
), t
RCD
= t
RCD
(I
CC
);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as I
DAD6W
675
650
mA
I
CC2P
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
25
25
mA
I
CC2Q
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
225
200
mA
I
CC2N
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
250
225
mA
I
CC3P
Active power-down current;
All banks open; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
150
125
mA
Slow PDN Exit MRS(12) = 1
50
50
mA
I
CC3N
Active standby current;
All banks open; t
CK
= t
CK
(I
CC
), t
RAS
= t
RASMAX
(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
300
250
mA
I
CC4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
= t
RASMAX
(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
1,025
800
mA
I
CC4R
Operating burst read current;
All banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
=
t
RASMAX
(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as I
DAD6W
975
775
mA
I
CC5
Burst auto refresh current;
t
CK
= t
CK
(I
CC
); Refresh command at every t
RFC
(I
CC
) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,050
1,000
mA
I
CC6
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
25
25
mA
I
CC7
Operating bank interleave read current;
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = t
RC
D(I
CC
)-1*t
CK
(I
CC
); t
CK
= t
CK
(I
CC
), t
RC
=
t
RC
(I
CC
), t
RRD
= t
RRD
(I
CC
), t
RCD
= 1*t
CK
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as I
DAD6R
; Refer to the following page for
detailed timing conditions
1,700
1,700
mA
W3H32M72E-XSBX
26
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC TIMING PARAMETERS
-55C T
A
< +125C; V
CCQ
= + 1.8V 0.1V, V
CC
= +1.8V 0.1V
Parameter
Symbol
533Mbs CL4
400Mbs CL3
Unit
Min
Max
Min
Max
Clock
Clock cycle time
CL=4
t
CK
(4)
3,750
8,000
5,000
8,000
ps
CL=3
t
CK
(3)
5,000
8,000
5,000
8,000
ps
CK high-level width
t
CH
0.48
0.52
0.48
0.59
t
CK
CK low-level width
t
CL
0.48
0.52
0.48
0.59
t
CK
Half clock period
t
HP
MIN (t
CH
,
t
CL
)
MIN (t
CH
,
t
CL
)
ps
Data
DQ output access time from CK/CK#
t
AC
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
t
HZ
t
AC(MAX)
t
AC(MAX)
ps
Data-out low-impedance window from CK/CK#
t
LZ
t
AC(MN)
t
AC(MAX)
t
AC(MN)
t
AC(MAX)
ps
DQ and DM input setup time relative to DQS
t
DS
100
150
DQ and DM input hold time relative to DQS
t
QH
225
275
DQ and DM input pulse width (for each input)
t
DIPW
0.35
0.35
t
CK
Data hold skew factor
t
QHS
400
450
ps
DQ-DQS hold, DQS to fi rst DQ to go nonvalid, per access
t
HQ
t
HP
- t
QHS
t
HP
- t
QHS
ps
Data valid output window (DVW)
t
DVW
t
QH
- t
DQSQ
t
QH
- t
DQSQ
ns
Data Strobe
DQS input high pulse width
t
DQSH
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
t
CK
DQS output access time fromCK/CK#
t
DQSCK
-450
+450
-500
+500
Ps
DQS falling edge to CK rising - setup time
t
DSS
0.2
0.2
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.2
0.2
t
CK
O DQS-DQ skew, DOS to last DQ valid, per group, per access
t
DQSQ
300
350
ps
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK
DQS write preamble setup time
t
WPRES
0
0
ps
DQS write preamble
t
WPRE
0.25
0.25
t
CK
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK
Write command to fi rst DQS latching transition
t
DQSS
WL-T
DQSS
WL+T
DQSS
WL-T
DQSS
WL+T
DQSS
t
CK
W3H32M72E-XSBX
27
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC TIMING PARAMETERS (continued)
-55C T
A
< +125C; V
CCQ
= + 1.8V 0.1V, V
CC
= +1.8V 0.1V
Parameter
Symbol
533Mbs CL4
400Mbs CL3
Unit
Min
Max
Min
Max
Command and
Address
Address and control input pulse width for each input
t
IPW
0.6
0.6
t
CK
Address and control input setup time
t
ISa
500
600
ps
t
ISb
250
350
ps
Address and control input hold time
t
IHa
500
600
ps
t
IHb
375
475
ps
CAS# to CAS# command delay
t
CCD
2
2
ps
ACTIVE to ACTIVE (same bank) command
t
RC
55
55
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
10
10
ns
ACTIVE to READ or WRITE delay
t
RCD
15
15
ns
Four Bank Activate period
t
FAW
50
50
ns
ACTIVE to PRECHARGE command
t
RAS
40
70,000
40
70,000
ns
Internal READ to precharge command delay
t
RTP
7.5
7.5
ns
Write recovery time
t
WR
15
15
ns
Auto precharge write recovery + precharge time
t
DAL
t
WR
+ t
RP
t
WR
+ t
RP
ns
Internal WRITE to READ command delay
t
WTR
7.5
10
ns
PRECHARGE command period
t
RP
15
15
ns
PRECHARGE ALL command period
t
RPA
t
RP
+ t
CK
t
RP
+ t
CK
ns
LOAD MODE command cycle time
t
MRD
2
2
t
CK
CKE low to CK, CK# uncertainty
t
DELAY
t
IS
+t
IH
+ t
CK
t
IS
+t
IH
+ t
CK
ns
Self Refresh
REFRESH to Active or Refresh to Refresh command interval
t
RFC
105
70,000
105
70,000
ns
Average periodic refresh interval
t
REFI
7.8
7.8
ns
Exit self refresh to non-READ command
t
XSNR
t
RPC(MIN)
+ 10
t
RFC(MIN)
+ 10
ns
Exit self refresh to READ
t
XSRD
200
200
t
CK
Exit self refresh timing reference
t
lSXR
t
IS
t
IS
ps
ODT
ODT tum-on delay
t
AOND
2
2
2
2
t
CK
ODT turn-on
t
ACN
t
AC(MIN)
t
AC(MAX)
+ 1000
t
AC(MIN)
t
AC(MAX)
+ 1000
ps
ODT turn-off delay
t
AOFD
2.5
2.5
2.5
2.5
t
CK
ODT tum-off
t
AOF
t
AC(MIN)
t
AC(MAX)
+
600
t
AC(MIN)
t
AC(MAX)
+
600
ps
ODT tum-on (power-down mode)
t
AONPD
t
AC(MIN)
+
2000
2 x t
CK
+
t
AC(MAX)
+ 1000
t
AC(MIN)
+
2000
2 x t
CK
+
t
AC(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
t
AOFPD
t
AC(MIN)
+
2000
2 x t
CK
+
t
AC(MAX)
+ 1000
t
AC(MIN)
+
2000
2 x t
CK
+
t
AC(MAX)
+ 1000
ps
ODT to power-down entry latency
t
ANPD
3
3
t
CK
ODT power-down exit latency
t
AXPD
8
8
t
CK
Power-Down
Exit active power-down to READ command, MR[bit12=0]
t
XARD
2
2
t
CK
Exit active power-down to READ command, MR[bit12=1]
t
XARDS
6-AL
6-AL
t
CK
Exit precharge power-down to any non-READ command
t
XP
2
2
t
CK
CKE minimum high/low time
t
CKE
3
3
t
CK
W3H32M72E-XSBX
28
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
All linear dimensions are millimeters and parenthetically in inches
BOTTOM VIEW
PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
11 10 9 8 7 6 5 4 3 2 1
208 x 0.60 (0.024) NOM
1.0 (0.039)NOM
10.0 (0.394) NOM
18.15 (0.715) MAX
20.15 (0.793) MAX
18.0 (0.709) NOM
1.0 (0.039) NOM
3.20 (0.126) MAX
0.50
(0.020)
NOM
W3H32M72E-XSBX
29
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
WHITE ELECTRONIC DESIGNS CORP.
DDR2 SDRAM
CONFIGURATION, 32M x 72
1.8V Power Supply
DATA RATE (Mbs)
400 = 400Mbs CL3
533 = 533Mbs CL4
667 = 667Mbs
(2)
CL5
Blank = No data rate specifi ed for ES product
(1)
PACKAGE:
ES = Non Qualifi ed Product
(1)
SB = 208 Plastic Ball Grid Array (PBGA)
DEVICE GRADE:
M = Military
-55C to +125C
I
= In dus tri al -40C
to
+85C
C = Com
mer cial 0C
to
+70C
Blank = No temperature specifi ed for ES product
(1)
W 3H 32M 72 E - XXX SB X
Note 1: W3H32M72E-ESSB is the only available product until completion of qualifi cation.
2: Data rate of 667Mbs is advanced, contact factory for future availability.
W3H32M72E-XSBX
30
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Document Title
32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
September 2005
Advanced
Rev 1
Changes (Pg. 1, 3, 6)
1.1 Add pinout
November 2005
Advanced
Rev 2
Change (Pg. All)
2.1 Change status to Preliminary
2.2 Add additional functional information
February 2006
Preliminary
PDF 
ZIP