W3HG64M72EER-AD7
December 2005
Rev. 1
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
512MB 64Mx72 DDR2 SDRAM REGISTERED, w/PLL,
VLP Mini-DIMM
DESCRIPTION
The W3HG64M72EER is a 64Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
Vendor source control options
Industrial temperature option
Parity
option
FEATURES
244-pin, very low profi le dual in-line memory
module (VLP Mini-DIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300*, and PC2-6400*
Supports ECC error detection and correction
V
CC
= V
CCQ
= 1.8V 0.1V
V
CCSPD
= 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL)
Posted CAS# additive latency (AL)
On-die termination (ODT)
Programmable burst lenghts: 4 or 8
Serial Presence Detect (SPD) with EEPROM
Auto and Self Refresh Capability (64ms: 8,192
cycle refresh)
Gold (Au) edge contacts
RoHS
compliant
Single
Rank
Package
option
244 Pin Mini-DIMM
PCB 18.29mm (0.72")
OPERATING FREQUENCIES
PC2-3200
PC2-4200
PC2-5300*
PC2-6400*
Clock Speed
200MHz
266MHz
333MHz
400MHz
CL-t
RCD
-t
RP
3-3-3
4-4-4
5-5-5
6-6-6
* Contact factory for availability
W3HG64M72EER-AD7
December 2005
Rev. 1
ADVANCED
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PIN NAMES
Pin Name
Function
A0-A13
Address Inputs
BA0,BA1
SDRAM Bank Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check Bits
DQS0-DQS8
Data strobes
DQS0#-DQS8#
Data strobes complement
ODT0
On-die termination control
CK0,CK0#
Clock Inputs, positive line
CKE0
Clock Enables
S0#
Chip Selects
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
RESET#
Register Reset Input
DM (0-8)
Data Masks
V
CCSPD
SPD Power
V
CC
Core Power
V
CCQ
I/O Power
A10/AP
Address Input/Auto Precharge
V
SS
Ground
PAR_IN
Parity bit for the addess and control bus
ERR_OUT
Parity error found on the address and
control bus
SA0-SA2
SPD address
SDA
SPD Data Input/Output
SCL
Clock Input
NC
No connect
V
REF
Input/Output Reference
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1
V
REF
62
A4
123
V
SS
184
V
CCQ
2
V
SS
63
V
CCQ
124
DQ4
185
A3
3
DQ0
64
A2
125
DQ5
186
A1
4
DQ1
65
V
CC
126
V
SS
187
V
CC
5
V
SS
66
V
SS
127
DM0
188
CK0
6
DQS0#
67
V
SS
128
NC
189
CK0#
7
DQS0
68
NC/PAR_IN
129
V
SS
190
V
CC
8
V
SS
69
V
CC
130
DQ6
191
A0
9
DQ2
70
A10/AP
131
DQ7
192
BA1
10
DQ3
71
BA0
132
V
SS
193
V
CC
11
V
SS
72
V
CC
133
DQ12
194
RAS#
12
DQ8
73
WE#
134
DQ13
195
V
CCQ
13
DQ9
74
V
CCQ
135
V
SS
196
S0#
14
V
SS
75
CAS#
136
DM1
197
V
CCQ
15
DQS1#
76
V
CCQ
137
NC
198
ODT0
16
DQS1
77
NC
138
V
SS
199
A13
17
V
SS
78
NC
139
NC
200
V
CC
18
RESET#
79
V
CCQ
140
NC
201
NC
19
NC
80
NC
141
V
SS
202
V
SS
20
V
SS
81
V
SS
142
DQ14
203
DQ36
21
DQ10
82
DQ32
143
DQ15
204
DQ37
22
DQ11
83
DQ33
144
V
SS
205
V
SS
23
V
SS
84
V
SS
145
DQ20
206
DM4
24
DQ16
85
DQS4#
146
DQ21
207
NC
25
DQ17
86
DQS4
147
V
SS
208
V
SS
26
V
SS
87
V
SS
148
DM2
209
DQ38
27
DQS2#
88
DQ34
149
NC
210
DQ39
28
DQS2
89
DQ35
150
V
SS
211
V
SS
29
V
SS
90
V
SS
151
DQ22
212
DQ44
30
DQ18
91
DQ40
152
DQ23
213
DQ45
31
DQ19
92
DQ41
153
V
SS
214
V
SS
32
V
SS
93
V
SS
154
DQ28
215
DM5
33
DQ24
94
DQS5#
155
DQ29
216
NC
34
DQ25
95
DQS5
156
V
SS
217
V
SS
35
V
SS
96
V
SS
157
DM3
218
DQ46
36
DQS3#
97
DQ42
158
NC
219
DQ47
37
DQS3
98
DQ43
159
V
SS
220
V
SS
38
V
SS
99
V
SS
160
DQ30
221
DQ52
39
DQ26
100
DQ48
161
DQ31
222
DQ53
40
DQ27
101
DQ49
162
V
SS
223
V
SS
41
V
SS
102
V
SS
163
CB4
224
NC
42
CB0
103
SA2
164
CB5
225
NC
43
CB1
104
NC
165
V
SS
226
V
SS
44
V
SS
105
V
SS
166
DM8
227
DM6
45
DQS8#
106
DQS6#
167
NC
228
NC
46
DQS8
107
DQS6
168
V
SS
229
V
SS
47
V
SS
108
V
SS
169
CB6
230
DQ54
48
CB2
109
DQ50
170
CB7
231
DQ55
49
CB3
110
DQ51
171
V
SS
232
V
SS
50
V
SS
111
V
SS
172
NC
233
DQ60
51
NC
112
DQ56
173
V
CCQ
234
DQ61
52
V
CCQ
113
DQ57
174
NC
235
V
SS
53
CKE0
114
V
SS
175
V
CC
236
DM7
54
V
CC
115
DQS7#
176
NC
237
NC
55
NC
116
DQS7
177
NC
238
V
SS
56
NC/ERR_
OUT
117
V
SS
178
V
CCQ
239
DQ62
57
V
CCQ
118
DQ58
179
A12
240
DQ63
58
A11
119
DQ59
180
A9
241
V
SS
59
A7
120
V
SS
181
V
CC
242
SDA
60
V
CC
121
SA0
182
A8
243
SCL
61
A5
122
SA1
183
A6
244
V
CCSPD
W3HG64M72EER-AD7
December 2005
Rev. 1
ADVANCED
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/
RDQS
RS0#
DQS0
DQS0#
DM0
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/
RDQS
DQS4
DQS4#
DM4
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/
RDQS
DQS1
DQS1#
DM1
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/
RDQS
DQS5
DQS5#
DM5
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/
RDQS
DQS2
DQS2#
DM2
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/
RDQS
DQS6
DQS6#
DM6
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/
RDQS
DQS3
DQS3#
DM3
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/
RDQS
DQS7
DQS7#
DM7
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/
RDQS
DQS8
DQS8#
DM8
CS# DQS DQS#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
Serial PD
A1
A2
SA0 SA1 SA2
SCL
SDA
WP
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
Serial PD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
P
L
L
OE
CK0
CK0#
RESET#
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
Register
R
E
G
I
S
T
E
R
RST#
S0#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
CK
CK#
RS0#
S0# DDR2 SDRAMs
RBA0 - RBA1
BA0 - BA1 DDR2 SDRAMs
RA0 - RA13
A0 - A13 DDR2 SDRAMs
RRAS#
RAS# DDR2 SDRAMs
RCAS#
RCAS# DDR2 SDRAMs
RWE#
WE# DDR2 SDRAMs
RCKE0
CKE0 DDR2 SDRAMs
RODT0
ODT0 DDR2 SDRAMs
NOTE: All resistor values are 22 ohms 5% unless otherwise specifi ed.
W3HG64M72EER-AD7
December 2005
Rev. 1
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
V
CC
1 .7
1 .8
1 .9
V
1
I/O Supply voltage
V
CCQ
1 .7
1 .8
1 .9
V
4
V
CCL
Supply voltage
V
CCL
1 .7
1 .8
1 .9
V
4
I/O Reference voltage
V
REF
0.49 x V
CCQ
0.50 x V
CCQ
0.51 x V
CCQ
V
2
I/O Termination voltage
V
TT
V
REF
-0.04
V
REF
V
REF
+ 0.04
V
3
Notes:
1. V
CC
and V
CCQ
must track each other. V
CCQ
must be less than or equal to V
CC
.
2. V
REF
is expected to equal V
CCQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not excedd 1 percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed 2 percent of V
REF
(DC). This measurement is to be taken at the nearest V
REF
bypass capacitor.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
4. V
CCQ
tracks with V
CC
; V
CC
L track with V
CC
.
ABSOLUTE MAXIMUM DC RATINGS
Symbol
Parameter
MIN
MAX
U nit
V
CC
Voltage on V
CC
pin relative to V
SS
-1.0
2.3
V
V
CCQ
Voltage on V
CCQ
pin relative to V
SS
-0.5
2.3
V
V
CCL
Voltage on V
CCL
pin relative to V
SS
-0.5
2.3
V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
-0.5
2.3
V
T
STG
Storage temperature
-55
100
C
T
CASE
Device operating temperature
0
85
C
T
OPR
Operating temperature (ambient)
0
55
C
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V<V
IN
<0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
-5
5
A
CK, CK#
-5
5
A
DM
-5
5
A
I
OZ
Output leakage current;
0V<V
OUT
<V
CCQ
; DQs and ODT are disable
DQ, DQS, DQS#
-5
5
A
I
VREF
V
REF
leakage current; V
REF
= Valid V
REF
level
-18
18
A
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 - A1 3, BA0 - BA1 ,RAS#,CAS#,WE#)
C
IN1
pF
Input capacitance ( CKE0), (ODT0)
C
IN2
pF
Input capacitance (CS0#)
C
IN3
pF
Input capacitance (CK0, CK0#)
C
IN4
pF
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
C
IN5
pF
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
C
OUT1
pF
W3HG64M72EER-AD7
December 2005
Rev. 1
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature
T
OPER
0C to 85C
C
V
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85C, operation temperature range, all DRAM specifi cation will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1 ) Voltage
V
IH
(DC)
V
REF
+ 125
V
REF
+ 300
mV
Input Low (Logic 0) Voltage
V
IL
(DC)
-300
V
REF
- 125
mV
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1 ) Voltage (DDR2-400/533)
V
IH
(AC)
V
REF
+ 250
--
mV
AC Input High (Logic 1) Voltage (DDR2-667)
V
IH
(AC)
V
REF
+ 200
mV
AC Input Low (Logic 0) Voltage
V
IL
(AC)
--
V
REF
- 250
mV
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