W3HG128M64EEU-D4
March 2006
Rev. 0
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
1GB 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
DESCRIPTION
The W3HG128M64EEU is a 128Mx64 Double Data Rate
2 SDRAM memory module based on 1Gb DDR2 SDRAM
components. The module consists of eight 128Mx8, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
Vendor source control options
Industrial temperature option
FEATURES
200-pin, Small-Outline DIMM (SO-DIMM), Raw
Card "B"
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
V
CC
= V
CCQ
= 1.8V 0.1V
V
CCSPD
= 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit
prefetch
architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-Die
Termination
(ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Single
Rank
RoHS
Compliant
JEDEC
Package
option
200 Pin (SO-DIMM)
PCB 29.20mm (1.150") TYP
OPERATING FREQUENCIES
PC2-6400*
PC2-5300*
PC2-4200
PC2-3200
Clock Speed
400MHz
333MHz
266MHz
200MHz
CL-t
RCD
-t
RP
6-6-6
5-5-5
4-4-4
3-3-3
* Consult factory for availability
W3HG128M64EEU-D4
March 2006
Rev. 0
ADVANCED
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PIN NAMES
SYMBOL
DESCRIPTION
A0 - A13
Address input
ODT0
On-Die Termination
CK0, CK0#
Differential Clock Inputs
CK1, CK1#
Differential Clock inputs
CKE0
Clock Enable input
CS0#
Chip select
RAS#, CAS#, WE# Command Inputs
BA0 - BA2
Bank Address Inputs
DM0 - DM7
Input Data Mask
DQ0 - DQ63
Data Input/Output
DQS0 - DQS7
DQS0#-DQS7#
Data Strobe
SCL
Serial Clock for Presence Detect
SA0-SA1
Presence Detect Address Inputs
SDA
Serial Presence Detect Data
V
CC
Power Supply
V
REF
SSTL_18 reference voltage
V
SS
Ground
V
CCSPD
Serial EEPROM Power Supply
NC
No Connect
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
DQS2
101
A1
151
DQ42
2
V
SS
52
DM2
102
A0
152
DQ46
3
V
SS
53
V
SS
103
V
CC
153
DQ43
4
DQ4
54
V
SS
104
V
CC
154
DQ47
5
DQ0
55
DQ18
105
A10/AP
155
V
SS
6
DQ5
56
DQ22
106
BA1
156
V
SS
7
DQ1
57
DQ19
107
BA0
157
DQ48
8
V
SS
58
DQ23
108
RAS#
158
DQ52
9
V
SS
59
V
SS
109
WE#
159
DQ49
10
DM0
60
V
SS
110
CS0#
160
DQ53
11
DQS0#
61
DQ24
111
V
CC
161
V
SS
12
V
SS
62
DQ28
112
V
CC
162
V
SS
13
DQS0
63
DQ25
113
CAS#
163
NC
14
DQ6
64
DQ29
114
ODT0
164
CK1
15
V
SS
65
V
SS
115
NC
165
V
SS
16
DQ7
66
V
SS
116
A13
166
CK1#
17
DQ2
67
DM3
117
V
CC
167
DQS6#
18
V
SS
68
DQS3#
118
V
CC
168
V
SS
19
DQ3
69
NC
119
NC
169
DQS6
20
DQ12
70
DQS3
120
NC
170
DM6
21
V
SS
71
V
SS
121
V
SS
171
V
SS
22
DQ13
72
V
SS
122
V
SS
172
V
SS
23
DQ8
73
DQ26
123
DQ32
173
DQ50
24
V
SS
74
DQ30
124
DQ36
174
DQ54
25
DQ9
75
DQ27
125
DQ33
175
DQ51
26
DM1
76
DQ31
126
DQ37
176
DQ55
27
V
SS
77
V
SS
127
V
SS
177
V
SS
28
V
SS
78
V
SS
128
V
SS
178
V
SS
29
DQS1#
79
CKE0
129
DQS4#
179
DQ56
30
CK0
80
NC
130
DM4
180
DQ60
31
DQS1
81
V
CC
131
DQS4
181
DQ57
32
CK0#
82
V
CC
132
V
SS
182
DQ61
33
V
SS
83
NC
133
V
SS
183
V
SS
34
V
SS
84
NC
134
DQ38
184
V
SS
35
DQ10
85
BA2
135
DQ34
185
DM7
36
DQ14
86
NC
136
DQ39
186
DQS7#
37
DQ11
87
V
CC
137
DQ35
187
V
SS
38
DQ15
88
V
CC
138
V
SS
188
DQS7
39
V
SS
89
A12
139
V
SS
189
DQ58
40
V
SS
90
A11
140
DQ44
190
V
SS
41
V
SS
91
A9
141
DQ40
191
DQ59
42
V
SS
92
A7
142
DQ45
192
DQ62
43
DQ16
93
A8
143
DQ41
193
V
SS
44
DQ20
94
A6
144
V
SS
194
DQ63
45
DQ17
95
V
CC
145
V
SS
195
SDA
46
DQ21
96
V
CC
146
DQS5#
196
V
SS
47
V
SS
97
A5
147
DM5
197
SCL
48
V
SS
98
A4
148
DQS5
198
SA0
49
DQS2#
99
A3
149
V
SS
199
V
CCSPD
50
NC
100
A2
150
V
SS
200
SA1
W3HG128M64EEU-D4
March 2006
Rev. 0
ADVANCED
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
A0
Serial PD
A1
A2
SA0 SA1
SDA
SCL
WP
V
CCSPD
V
CC
V
REF
V
SS
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs, EEPROM
CS0#
3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS0#
DQS0
DM0
DM CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS4#
DQS4
DM4
DM CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS1#
DQS1
DM1
DM CS# DQS DQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2#
DQS2
DM2
DM CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6#
DQS6
DM6
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS3#
DQS3
DM3
DM CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS7#
DQS7
DM7
DM CS# DQS DQS#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
BA0-BA2: DDR2 SDRAMs
A0-A13: DDR2 SDRAMs
RAS#: DDR2 SDRAMs
CAS#: DDR2 SDRAMs
WE#: DDR2 SDRAMs
CKE0: DDR2 SDRAMs
ODT0: DDR2 SDRAMs
3
DDR2 SDRAMs x 4
CK0
CK0#
DDR2 SDRAMs x 4
CK1
CK1#
100
100
NOTE: 1. All resistor values are 22 ohm unless otherwise specifi ed.
W3HG128M64EEU-D4
March 2006
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Units
Notes
Supply Voltage
V
CC
1.7
1.9
V
-
I/O Reference Voltage
V
REF
0.49 x V
CC
0.51 x V
CC
V
1
I/O Termination Voltage (system)
V
TT
V
REF
- 40
V
REF
+ 40
mV
2
NOTE:
1. V
REF
is expected to equal V
CCQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V
REF
may not exceed
1 percent of the DC value. Peak-to-peak AC noise on V
REF
may not exceed 2 percent of V
REF
(DC). This measurement is to be taken at the nearest V
REF
bypass capacitor.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal
to V
REF
and must track variations in the DC level of V
REF
.
ABSOLUTE MAXIMUM DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
V
CC
V
CC
Supply Voltage Relative to V
SS
-0.5
2.3
V
V
IN
, V
OUT
Voltage on any Pin Relative to V
SS
-0.5
2.3
V
T
STG
Storage Temperature
-55
100
C
T
CASE
DDR2 SDRAM Device Operating Temperature*
0
85
C
T
OPR
Operating Temperature (Ambient)
0
65
C
I
I
Input Leakage Current; Any input 0V V
IN
V
CC
;
V
REF
input 0V V
IN
0.95V; (All other pins not under
test = 0V)
Command/Address,
RAS#, CAS#, WE# S#,
CKE
-40
40
A
CK, CK#
-20
20
DM
-5
5
I
OZ
Output Leakage Current; 0V V
OUT
V
CC
Q; DQs
and ODT are disabled
DQ, DQS, DQS#
-5
5
A
I
VREF
V
REF
Leakage Current; V
REF
= Valid V
REF
level
-16
16
A
* T
CASE
specifi es as the temperature at the top center of the memory devices.
CAPACITANCE
T
A
= 25C, f = 100MHz, V
CC
= 1.8V, V
REF
= V
SS
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
35
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
35
pF
Input Capacitance (CKE0)
C
IN3
31
pF
Input Capacitance (CK0, CK0#)
C
IN4
15
pF
Input Capacitance (CS0#)
C
IN5
31
pF
Input Capacitance (DQS0#-DQS17#)
C
IN6
6
pF
Input Capacitance (BA0-BA1)
C
IN7
35
pF
Data input/output Capacitance (DQ0-DQ63)
C
OUT
6
pF
NOTE:
* These capacitance values are based on worst case component values in conjunction with the circuit boards associated parasitic net capacitance.
W3HG128M64EEU-D4
March 2006
Rev. 0
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
V
CC
= +1.8V 0.1V
Parameter
Symbol Condition
806
665
534
403
Units
Operating one device
bank active-precharge
current;
I
CC0
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
MIN (I
CC
); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
TBD
800
640
640
mA
Operating one device
bank active-read-
precharge current;
I
CC1
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
),
t
RAS
= t
RAS
MIN (I
CC
), t
RCD
= t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as I
CC4W
.
TBD
1,160
760
760
mA
Precharge power-down
current;
I
CC2P
All device banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
TBD
56
40
40
mA
Precharge quiet
standby current;
I
CC2Q
All device banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
TBD
480
328
280
mA
Precharge standby
current;
I
CC2N
All device banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
TBD
520
360
280
mA
Active power-down
current;
I
CC3P
All device banks open; t
CK
= t
CK
(I
CC
); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
TBD
320
240
200
mA
Slow PDN Exit
MR[12] = 1
TBD
80
80
80
mA
Active standby current;
I
CC3N
All device banks open; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
MAX (I
CC
), t
RP
= t
RP
(I
CC
);
CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
560
400
320
mA
Operating burst write
current;
I
CC4W
All device banks open, Continuous burst writes; BL = 4, CL = CL (I
CC
),
AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
MAX (I
CC
), t
RP
= t
RP
(I
CC
); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
TBD
1,440
1,040
960
mA
Operating burst read
current;
I
CC4R
All device banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL
= CL (I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
MAX (I
CC
), t
RP
= t
RP
(I
CC
);
CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
1,640
1,160
1,080
mA
Burst refresh current;
I
CC5
t
CK
= t
CK
(I
CC
); Refresh command at every t
RFC
(I
CC
) interval; CKE
is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
2,160
2,000
1,920
mA
Self refresh current;
I
CC6
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
TBD
56
40
40
mA
Operating device bank
interleave read current;
I
CC7
All device banks interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL (I
CC
),
AL = t
RCD
(I
CC
)-1 x t
CK
(I
CC
); t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RRD
= t
RRD
(I
CC
),
t
RCD
= t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING
TBD
2,720
2,360
2,360
mA
Note:
I
CC
specifi cation is based on MICRON components. Other DRAM manufacturers specifi cation may be different.
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