1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
Access Times of 90, 100, 120ns
Packaging
159 PBGA, 13x22mm - 1.27mm pitch
1,000,000 Erase/Program Cycles
Sector
Architecture
Bank 1 (4Mb): eight 4K word, eight 32K word
Bank 2 (12Mb): twenty-four 32K word
Bank 3 (12Mb): twenty-four 32K word
Bank 4 (4Mb): eight 32K word
Bottom
boot
block
Zero
Power
Operation
Organized as 2Mx64 or 2x2Mx32
Commercial,
Industrial
and
Military
Temperature
Ranges
3.3 Volt for Read and Write Operations
Simultaneous
Read/Write
Operation:
Data can be continuously read from one bank
while executing erase/program functions in
another bank
Zero latency between read and write operations
Erase
Suspend/Resume
Suspends erase operations to allow programming
in same bank
Data#
Polling
and
Toggle
Bits
Provides a software method of detecting the
status of program or erase cycles
Unlock
Bypass
Program
command
Reduces overall programming time when issuing
multiple program command sequences
Ready/Busy# output (RY/BY#)
Hardware method for detecting program or erase
cycle completion
Hardware reset pin (RESET#)
Hardware method of resetting the internal state
machine to the read mode
WP#/A
CC
input pin
Write protect (WP#) function allows protection
two outermost boot sectors, regardless of sector
protect status
Acceleration (A
CC
) function accelerates program
timing
Sector
Protection
Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within
that sector
Temporary Sector Unprotect allows changing
data in protected sectors in-system
Note: For programming information refer to Flash Programming
W72M64V-XBX Application Note.
This product is subject to change without notice.
FEATURES
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
FIGURE 1: PIN CONFIGURATION FOR W72M64V-XBX
Top View
1
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
GND
A2
WP#/A
CC
A11 GND V
CC
A7 A10 A15 GND*
GND
OE#
A0
DNU*
V
CC
A12 A16 DNU* A20 GND
GND
CS3#
DQ34
DQ36
DQ38
CS4#
DQ50
DQ52
DQ54
GND
V
CC
DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62 V
CC
V
CC
DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55 V
CC
V
CC
DQ33 DQ43 DQ45 DQ47 DQ49 DQ59 DQ61 DQ63 V
CC
V
CC
GND DQ41
WE3# V
CC
DQ57 DNU WE4# V
CC
V
CC
GND
GND
GND
V
CC
V
CC
GND GND GND V
CC
V
CC
GND GND GND V
CC
V
CC
GND GND GND V
CC
V
CC
V
CC
DQ25 DQ27 DQ22 CS1# DQ2 DQ12 GND V
CC
V
CC
CS2#
DQ18 DQ20 DQ30 DQ0 DQ10 DQ5 DQ14 V
CC
V
CC
DQ16 DQ26 DQ28 DQ23 DQ8 DQ3 DQ13 DQ7 V
CC
V
CC
DQ24 DQ19 DQ21 DQ31 DQ1 DQ11 DQ6 DQ15 V
CC
GND
DQ17 WE2#
DQ29
DNU
DQ9
DQ4
WE1#
A19
GND
GND
A4
A17
RY/BY# GND A14
A5 A18
A8 GND
GND
A3
A6
A9
V
CC
GND A1 RESET# A13 GND
* Ball G8 is reserved for A
21
and ball G4 is reserved for A
22
on
W78M64V-XSBX.
Pin Description
DQ0-63
Data Inputs/Outputs
A0-20
Address Inputs
WE1-4#
Write Enables
CS1-4#
Chip Selects
OE#
Output Enable
RESET#
Hardware Reset
WP#/ACC
Hardware Write
Protect/Acceleration
RY/BY#
Ready/Busy Output
V
CC
Power Supply
GND
Ground
DNU
Do Not Use
Block Diagram
DQ
0-15
DQ
16-31
DQ
32-47
DQ
48-63
CS
1
#
CS
2
#
CS
3
#
CS
4
#
2M x 16
2M x 16
2M x 16
2M x 16
BYTE#
BYTE#
BYTE#
BYTE#
WE
4
#
WE
3
#
WE
2
#
WE
1
#
WP#/ACC
V
CC
A
0-20
RY/BY#
RESET#
OE#
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Operating Temperature
-55 to +125
C
Supply Voltage Range (V
CC
)
-0.5 to +4.0
V
Signal Voltage Range
-0.5 to Vcc +0.5
V
Storage Temperature Range
-55 to +150
C
Endurance (write/erase cycles)
1,000,000 min.
cycles
NOTES:
1.
Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
3.0
3.6
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Operating Temp. (Ind.)
T
A
-40
+85
C
CAPACITANCE
T
A
= +25C, F = 1.0MHz
Parameter
Symbol
Max
Unit
WE1-4# capacitance
C
WE
8 pF
CS1-4# capacitance
C
CS
8
pF
Data I/O capacitance
C
I/O
10
pF
Address input capacitance
C
AD
30
pF
RESET# capacitance
C
RS
26
pF
RY/BY# capacitance
C
RB
26
pF
OE# capacitance
C
OE
32
pF
This parameter is guaranteed by design but not tested.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
Pattern Data
Retention Time
150C
10
Years
125C
20
Years
DC CHARACTERISTICS CMOS COMPATIBLE
V
CC
= 3.3V 0.3V, -55C T
A
+125C
Parameter
Symbol
Conditions
Min
Max Unit
Input Leakage Current
I
LI
V
CC
= 3.6V, V
IN
= GND to V
CC
-10
10
A
Output Leakage Current
I
LO
V
CC
= 3.6V, V
OUT
= GND to V
CC
-10
10
A
V
CC
Active Current for Read (1)
I
CC1
CS# = V
IL
#, OE = V
IH
, f = 5MHz
65
mA
V
CC
Active Current for Program or Erase (2,3)
I
CC2
CS# = V
IL
#, OE = V
IH
, WE# = V
IL
120
mA
V
CC
Standby Current (2)
I
CC3
CS# = RESET# = V
CC
0.3V
400
A
Automatic Sleep Mode (2,4,5)
I
CC5
V
IH
= V
CC
0.3V;
V
IL
= V
SS
0.3V
400
A
V
CC
Active Read-While-Program Current (1,2)
I
CC6
CS# = V
IL
#, OE = V
IH
180
mA
V
CC
Active Program-While-Erase Current (1,2)
I
CC7
CS# = V
IL
#, OE = V
IH
180
mA
V
CC
Active Program-While-Erase-Suspended Current (2,5)
I
CC8
CS# = V
IL
#, OE = V
IH
140
mA
A
CC
Accelerated Program Current
I
ACC
CS# = V
IL
#, OE = V
IH
ACC Pin
40
mA
VCC Pin
120
Input Low Voltage
V
IL
-0.5
0.8
V
Input High Voltage
V
IH
V
CC
= min
2.1
V
CC
+ 0.3
V
Voltage for WP#/A
CC
Sector
Protect/Unprotect and Program Acceleration
V
HH
V
CC
= 3.0V + 0.3V
8.5
9.5
V
Voltage for Autoselect and Temporary Sector Unprotect
V
ID
V
CC
= 3.0V + 0.3V
8.5
12.5
V
Output Low Voltage
V
OL
I
OL
= 4.0 mA, V
CC
= 3.0V
0.45
V
Output High Voltage
V
OH1
I
OH
= -2.0 mA, V
CC
= 3.0V
2.55
V
Low V
CC
Lock-Out Voltage (5)
V
LKO
2.3
2.5
V
NOTES:
1. The
I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 8 mA/MHz, with OE# at V
IH
.
2. Maximum
I
CC
specifi cations are tested with V
CC
= V
CC
MAX
3. I
CC
active while Embedded Algorithm (program or erase) is in progress.
4.
Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30ns.
5. Not
tested.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS CS# CONTROLLED
V
CC
= 3.3V 0.3V, -55C T
A
+125C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time (3)
t
AVAV
t
WC
90
100
120
ns
Write Enable Setup Time
t
WLEL
t
WS
0
0
0
ns
Chip Select Pulse Width
t
ELEH
t
CP
35
45
50
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
Data Setup Time
t
DVEH
t
DS
45
45
50
ns
Data Hold Time
t
EHDX
t
DH
0
0
0
ns
Address Hold Time
t
ELAX
t
AH
45
45
50
ns
Chip Select Pulse Width High (3)
t
EHEL
t
CPH
30
30
30
ns
Duration of Word Programming Operation (1)
t
WHWH1
300
300
300
s
Sector Erase Time (2)
t
WHWH2
5
5
5
sec
Read Recovery Time Before Write (3)
t
GHEL
0
0
0
ns
Chip Programming Time (4)
42
42
42
sec
NOTES:
1.
Typical value for t
WHWH
1
is 7s.
2.
Typical value for t
WHWH
2
is 0.4 sec.
3.
Guaranteed by design, but not tested.
4.
Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
FIGURE 2
Current Source
Current Source
I
OL
I
OH
C
EFF
= 50 pf
V
Z
1.5V
(Bipolar Supply)
D.U.T.
AC Test Circuit
AC Test Conditions
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 2.5
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS WE# CONTROLLED
V
CC
= 3.3V 0.3V, -55C T
A
+125C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time (3)
t
AVAV
t
WC
90
100
120
ns
Chip Select Setup Time (3)
t
ELWL
t
CS
0
0
0
ns
Write Enable Pulse Width
t
WLWH
t
WP
35
50
50
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
Data Setup Time
t
DVWH
t
DS
45
50
50
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
Address Hold Time
t
WLAX
t
AH
45
50
50
ns
Write Enable Pulse Width High (3)
t
WHWL
t
WPH
30
30
30
ns
Duration of Byte Programming Operation (1)
t
WHWH1
300
300
300
s
Sector Erase (2)
t
WHWH2
5
5
5
sec
Read Recovery Time before Write (3)
t
GHWL
0
0
0
ns
VCC Setup Time
t
VCS
50
50
50
s
Chip Programming Time (4)
42
42
42
sec
Address Setup Time to OE# low during toggle
bit polling
t
ASO
15
15
15
ns
Write Recovery Time from RY/BY# (3)
t
RB
0
0
0
ns
Program/Erase Valid to RY/BY#
t
BUSY
90
90
90
ns
NOTES:
1.
Typical value for t
WHWH
1
is 7s.
2.
Typical value for t
WHWH
2
is 0.4 sec.
3.
Guaranteed by design, but not tested.
4.
Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
AC CHARACTERISTICS READ-ONLY OPERATIONS
V
CC
= 3.3V 0.3V, -55C T
A
+125C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time (1)
t
AVAV
t
RC
90
100
120
ns
Address Access Time
t
AVQV
t
ACC
90
100
120
ns
Chip Select Access Time
t
ELQV
t
CE
90 100 120
ns
Output Enable to Output Valid
t
GLQV
t
OE
40
40 50
ns
Chip Select High to Output High Z
t
EHQZ
t
DF
20 20 20
ns
Output Enable High to Output High Z
t
GHQZ
t
DF
20 20 20
ns
Output Hold from Addresses, CS# or OE#
Change, Whichever occurs fi rst
t
AXQX
t
OH
0
0
0
ns
Output Enable Hold Time (1)
Read
t
OEH
0
0
0
Toggle and
Data# Polling
10
10
10
1.
Guaranteed by design, not tested.
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