1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Selection of Processor Speeds: 16.67, 20, 25 MHz
Military Temperature Range: -55C to +125C
Packaging
114 pin Ceramic PGA (P2)
132 lead Ceramic Quad Flatpack, CQFP (Q2)
Object-code compatible with earlier 68000
Microprocessors
Addressing mode extensions for enhanced support
of high-level languages
Bit
Field
Data
Type
Accelerates
Bit-Oriented
Applicationsi.e., Video Graphics
Fast
On-Chip
Instruction
Cache
Speeds
Instructions and Improves Bus Bandwidth
Coprocessor Interface to Companion 32-Bit
Peripheralsthe 68881 and 68882 Floating-Point
Coprocessors and the 68851 Paged Memory
Management Unit
Pipelined Architecture with High Degree of Internal
Parallelism allowing Multiple Instructions to be
executed concurrently
FIGURE 1 BLOCK DIAGRAM
High-Performance
Asynchronous
Bus
Is
Nonmultiplexed and Full 32-Bits
Dynamic Bus Sizing Effi ciently Supports 8-/16-/32-
Bit Memories and Peripherals
Full Support of Virtual Memory and Virtual Machine
16 32-Bit General-Purpose Data and Address
Registers
Two 32-Bit Supervisor Stack Pointers and Five
Special-Purpose Control Registers
18 Addressing Modes and 7 Data Types
4 GigaByte Direct Addressing Range
DESCRIPTION
The WC32P020 is a 32-bit implementation of the 68000
Family of microprocessors. Using HCMOS technology,
the WC32P020 is implemented with 32-bit registers and
data paths, 32-bit addresses, a powerful instruction set,
and fl exible addressing modes.
MICRO MACHINE
MICROROM
NANOROM
CONTROL SECTION
SEQUENCER
INSTRUCTION DECODE
INSTRUCTION PIPE
TAG
CACHE
INSTRUCTION
ADDRESS
SECTION
OPERAND
ADDRESS
SECTION
DATA
SECTION
EXECUTION UNIT
INSTRUCTION
CACHE
ADDRESS
PADS
BUS
CONTROLLER
DATA
PADS
BUS CONTROLLER
68020 FEATURES
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 2 PIN CONFIGURATION FOR WC32P020-XXM, CQFP (Q2)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
11
9
11
8
11
7
NC
BGAC#
BR#
A0
A1
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A
17
V
CC
V
CC
GND
GND
A16
A15
A14
A13
A12
A11
A10
NC
NC
NC
NC
NC
A9
A8
A7
A6
A5
A4
A3
A2
GND
OSC#
IPEND#
V
CC
V
CC
GND
GND
IPL2#
IPL1#
IPL0#
D0
D1
D2
D3
D4
GND
GND
V
CC
V
CC
D5
NC
NC
NC
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
GND
GND
V
CC
V
CC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
NC
NC
NC
NC
GND
BG#
V
CC
GND
GND
CLK
RESET#
V
CC
V
CC
RMC
FC0
FC1
FC2
SIZ0
SIZ1
DBEN#
ECS#
CDIS#
AV
E
C
#
DSACK0#
DSACK1#
BERR#
GND
GND
HAL
T
AS#
DS#
GND
GND
R/W#
NC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
FIGURE 3 PIN CONFIGURATION FOR WC32P020-XXM, PGA (P2)
TOP VIEW
D28
D29
R/W#
HALT#
BERR#
AVEC#
SIZ1
FC2
RMC#
V
CC
CLK
BG#
A1
D31
DS#
AS#
GND
DSACK1#
CDIS#
ECS#
SIZ0
FC0
V
CC
RESET#
GND
BGACK#
1 2 3 4 5 6 7 8 9 10 11 12 13
D25
D26
D30
GND
GND
DSACK0#
DBEN#
FC1
V
CC
V
CC
GND
BR#
A31
D22
D24
D27
A0
A30
A28
D20
D21
D23
A29
A27
A26
D17
D18
D19
A25
A24
A23
GND
D16
GND
A21
A20
A22
V
CC
V
CC
D15
A17
A18
A19
D14
D13
D11
A16
GND
V
CC
D12
D10
D7
A12
D15
GND
D9
D6
GND
A9
D13
A14
D8
D5
D3
D1
IPL0#
IPL2#
GND
GND
A2
A4
A7
A10
A11
V
CC
D4
D2
D0
IPL1#
GND
V
CC
IPEND#
OCS#
A3
A5
A6
A8
V
CC
N
M
L
K
J
H
G
F
E
D
C
B
A
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADDRESSING MODES
Addressing
Syntax
Register Direct
Data Register Direct
Address Register Direct
Dn
An
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
(An)
(An) +
- (An)
(d16,An)
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
(d8,An,Xn)
(bd,An,Xn)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
(d8,PC,Xn)
(bd,PC,Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
([bd,PC],Xn,od)
([bd,PC,Xn],od)
Absolute
Absolute Short
Absolute Long
(
xxx).W
(xxx).L
Immediate
#(data)
NOTES:
Dn = Data Register, DO-D7
An = Address Register, AO-A7
d8, d16 = A twos-complement or sign-extended displacement; added as part of the
effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted,
assemblers use a value of zero.
Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE,
where SIZE is.W or .L (indicates index register size) and SCALE is 1, 2, 4,
or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is
optional.
bd = A twos-complement base displacement; when present, size can be 16 or 32
bits.
od = 0uter displacement, added as part of effective address calculation after any
memory indirection, use is optional with a size of 16 or 32 bits.
PC = Program Counter
(data) = Immediate value of 8, 16, or 32 bits
( ) = Effective Address
[ ] = Use as indirect access to long-word address.
Mnemonic
Description
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CALLM
CAS
CAS2
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
Call Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
DBcc
DIVS, DIVSL
DIVU, DIVUL
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
EOR
EORI
EXG
EXT, EXTB
Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend
ILLEGAL
Take Illegal Instruction Trap
JMP
JSR
Jump
Jump to Subroutine
LEA
LINK
LSL, LSR
Load Effective Address
Link and Allocate
Logical Shift Left and Right
MOVE
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
MULS
MULU
Signed Multiply
Unsigned Multiple
INSTRUCTION SET
Mnemonic
Description
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
INSTRUCTION SET (cont'd)
Mnemonic
Description
NBCD
NEG
NEGX
NOP
NOT
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
OR
ORI
ORI CCR
ORI SR
Logical Inclusive OR
Logical Inclusive OR Immediate
Logical Inclusive OR Immediate to Condition Codes
Logical Inclusive OR Immediate to Status Register
PACK
PEA
Pack BCD
Push Effective Address
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore Codes
Return from Subroutine
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
TAS
TRAP
TRAPcc
TRAPV
TST
Test Operand and Set
Trap
Trap Conditionally
Trap on Overfl ow
Test Operand
UNLK
Unlink
UNPK
Unpack BCD
COPROCESSOR INSTRUCTIONS
Mnemonic
Description
cpBcc
Branch Conditionally
cpDBcc
Test Coprocessor Condition, Decrement and Branch
cpGEN
Coprocessor General Instruction
Mnemonic
Description
cpRESTORE
Restore Internal State of Coprocessor
cpSAVE
Save Internal State of Coprocessor
cpScc
Set Conditionally
cpTRAPcc
Trap Conditionally
FIGURE 4 FUNCTIONAL SIGNAL GROUPS
FC0-FC2
A0-A31
D0-D31
SIZ0
SIZ1
RESET#
HALT#
BERR#
CLK
Vcc (10)
GND (13)
INTERRUPT
PRIORITY
CDIS#
IPEND#
AVEC#
BR#
BG#
BGACK#
ECS#
OCS#
RMC#
AS#
DS#
R/W#
DBEN#
DSACK0#
DSACK1#
ASYNCHRONOUS
BUS CONTROL
INTERRUPT
CONTROL
IPL0#-IPL2#
BUS ARBITRATION
CONTROL
BUS EXCEPTION
CONTROL
TRANSFER
SIZE
CACHE
CONTROL
FUNCTION
CODES
ADDRESS
BUS
DATA
BUS
SIGNAL DESCRIPTION
The V
CC
and GND pins are separated into four groups
to provide individual power supply connections for the
address bus buffers, data bus buffers, and all other buffers
and internal logic. See FIGURE 4.
Group
V
CC
GND
Address Bus
A9, D3
A10, B9, C3, F12
Data Bus
M8, N8, N13
L7, L11, N7, K3
Logic
D1, D2, E3, G11, G13
G12, H13, J3, K1
Clock
--
B1
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
SIGNAL INDEX
Signal Name
Mnemonic
Function
Function Codes
FC2-FC0
3-bit function code used to identify the address space of each bus cycle.
Address Bus
A0-A31
32-bit address bus.
Data Bus
D0-D31
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle.
Size
SIZ0/SIZ1
Indicates the number of bytes remaining to be transferred for this cycle. These signals, together
with A1 and A0, defi ne the active sections of the data bus.
External Cycle Start
ECS#
Provides an indication that a bus cycle is beginning.
Operand Cycle Start
OCS#
Identical operation to that of ECS except that OCS is asserted only during the fi rst bus cycle of an
operand transfer.
Read,Write
R/W#
Defi nes the bus transfer as a processor read or write.
Read-Modify-Write Cycle
RMC#
Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation.
Address Strobe
AS#
Indicates that a valid address is on the bus.
Data Strobe
DS#
Indicates that valid data is to be placed on the data bus by an external device or has been placed
on the data bus by the WC32P020-XXM.
Data Buffer Enable
DBEN#
Provides an enable signal for external data buffers.
Data Transfer and Size
Acknowledge
DSACK0#/DSACK1#
Bus response signals that indicate the requested data transfer operation has completed. In
addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are
used for asynchronous transfers.
Interrupt Priority Level
IPL0#-IPL2#
Provides an encoded interrupt level to the processor.
Interrupt Pending
IPEND#
Indicates that an interrupt is pending.
Autovector
AVEC#
Requests an autovector during an interrupt acknowledge cycle.
Bus Request
BR#
Indicates that an external device requires bus mastership.
Bus Grant
BG#
Indicates that an external device may assume bus mastership.
Bus Grant Acknowledge
BGACK#
Indicates that an external device has assumed bus mastership.
Reset
RESET#
System reset.
Halt
HALT#
Indicates that the processor should suspend bus activity.
Bus Error
BERR#
Indicates that an erroneous bus operation is being attempted.
Cache Disable
CDIS#
Dynamically disables the on-chip cache to assist emulator support
Clock
CLK
Clock input to the processor.
Power Supply
Vcc
Power supply.
Ground
GND
Ground connection.
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