1
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
128Kx32 EEPROM MODULE, SMD 5962-94585
Top View
Block Diagram
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
128K x 8
8
I / O
0 - 7
W E
1
# CS
1
#
W E
2
# CS
2
#
W E
3
# CS
3
#
W E
4
# CS
4
#
128K x 8
8
I / O
8 - 1 5
128K x 8
8
I / O
1 6 - 2 3
128K x 8
8
I / O
2 4 - 3 1
A
0 - 1 6
O E #
FEATURES
Access Times of 120**, 140, 150, 200, 250, 300ns
Packaging:
66-pin, PGA Type, 27.3mm (1.075") square,
Hermetic Ceramic HIP (Package 400)
68 lead, 22.4mm sq. CQFP (G2T), 4.57mm
(0.180") high, (Package 509)
Organized as 128Kx32; User Confi gurable as
256Kx16 or 512Kx8
Write Endurance 10,000 Cycles
Data Retention Ten Years Minimum (at +25C)
Commercial, Industrial and Military Temperature
Ranges
Low
Power
CMOS
Automatic
Page
Write
Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5
Volt
Power
Supply
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WE128K32-XG2TX - 8 grams typical
WE128K32-XH1X - 13 grams typical
** 120ns not available for SMD product
*This product is subject to change without notice.
FIGURE 1 PIN CONFIGURATION FOR
WE128K32N-XH1X
Pin Description
I/O0-31
Data Input/Output
A0-16
Address Inputs
WE1-4#
Write Enable
CS1-4#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
2
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
FIGURE 3 PIN CONFIGURATION FOR WE128K32-XG2TX
Block Diagram
128K x 8
8
I / O
0 - 7
W E
1
# CS
1
#
W E
2
# CS
2
#
W E
3
# CS
3
#
W E
4
# CS
4
#
128K x 8
8
I / O
8 - 1 5
128K x 8
8
I / O
1 6 - 2 3
128K x 8
8
I / O
2 4 - 3 1
A
0 - 1 6
O E #
Top View
The WEDC 68 lead CQFP
fi lls the same fi t and function
as the JEDEC 68 lead CQFJ
or 68 PLCC. But it has the
TCE and lead inspection
advantage of the CQFP
form.
Pin Description
I/O0-31
Data Input/Output
A0-16
Address Inputs
WE1-4#
Write Enable
CS1-4#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
3
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 3
AC Test Circuit
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LOx32
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current (x32)
I
CCx32
CS# = V
IL
, OE# = V
IH
, f = 5MHz
250
mA
Standby Current
I
SB
CS# = V
IH
, OE# = V
IH
, f = 5MHz
2.5
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA, V
CC
= 4.5V
0.45
V
Output High Voltage
V
OH
I
OH
= -400A, V
CC
= 4.5V
2.4
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
TRUTH TABLE
CS#
OE#
WE#
Mode
Data I/O
H
X
X
Standby
High Z
L
L
H
Read
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
High Z/Data Out
X
X
H
Write
X
L
X
Inhibit
CAPACITANCE
T
A
= +25C
Parameter
Symbol
Conditions Max Unit
OE# capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
50
pF
WE1-4# capacitance
HIP
(PGA)
C
WE
V
IN
= 0 V, f = 1.0 MHz
20
pF
CQFP
G2T
20
CS1-4# capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
20
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
20
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
50
pF
This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Operating Temperature
T
A
-55 to +125
C
Storage Temperature
T
STG
-65 to +150
C
Signal Voltage Relative to GND
V
G
-0.6 to + 6.25
V
Voltage on OE# and A9
-0.6 to +13.5
V
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specifi cation is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.0
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.5
+0.8
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Operating Temp. (Ind.)
T
A
-40
+85
C
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
IOH
IOL
Current Source
Vz ~ 1.5V
Bipolar Supply
~
D.U.T
Ceff = 50 pf
4
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
WRITE
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs fi rst. A byte write operation will
automatically continue to completion.
write cycle timing
Figures 5 and 6 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150 sec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 sec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Write Cycle Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
t
WC
10
ms
Address Set-up Time
t
AS
0
ns
Write Pulse Width (WE# or CS#)
t
WP
100
ns
Chip Select Set-up Time
t
CS
0
ns
Address Hold Time
t
AH
100
ns
Data Hold Time
t
DH
10
ns
Chip Select Hold Time
t
CSH
0
ns
Data Set-up Time
t
DS
50
ns
Output Enable Set-up Time
t
OES
0
ns
Output Enable Hold Time
t
OEH
0
ns
Write Pulse Width High
t
WPH
50
ns
5
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
t
ADDRESS
CS
1-4
#
WE
1-4
#
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE#
t
WC
t
DS
t
ADDRESS
WE
1 - 4#
CS
1 - 4#
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE#
t
DS
t
WC
FIGURE 5 WRITE WAVEFORMS WE# CONTROLLED
FIGURE 6 WRITE WAVEFORMS CS# CONTROLLED
6
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
READ
The WE128K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE# are
low and WE# is high, this data is present on the outputs.
When CS# and OE# are high, the outputs are in a high
impedance state. This two line control prevents bus
contention.
Notes:
OE# may be delayed up to t
ACS
- t
OE
after the falling edge of CS# without impact
on t
OE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
AC READ CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Read Cycle Parameter
Symbol
-120
-140
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
120
140
150
200
250
300
ns
Address Access Time
t
ACC
120
140
150
200
250
300
ns
Chip Select Access Time
t
ACS
120
140
150
200
250
300
ns
Output Hold from Add. Change, OE# or CS#
t
OH
0
0
0
0
0
0
ns
Output Enable to Output Valid
t
OE
0
50
0
55
0
55
0
55
0
85
0
85
ns
Chip Select or OE# to High Z Output
t
DF
60
70
70
70
70
70
ns
FIGURE 7 READ WAVEFORMS
t
ADDRESS
CS#
OE#
OUTPUT
OH
t
DF
t
ACC
t
RC
t
OE
t
ACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DATA POLLING
The WE128K32-XXX offers a data polling feature which
allows a faster method of writing to the device. Figure 8
shows the timing diagram for this function. During a byte
or page write cycle, an attempted read of the last byte
written will result in the complement of the written data
on D7 (for each chip.) Once the write cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. Data polling may begin at any time during
the write cycle.
FIGURE 8 DATA POLLING WAVEFORMS
DATA POLLING CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C)
Parameter
Symbol
Min
Max
Unit
Data Hold Time
tDH
10
ns
OE# Hold Time
tOEH
10
ns
OE# To Output Valid
tOE
55
ns
Write Recovery Time
tWR
0
ns
WE
1-4
#
t
OEH
t
DH
t
OE
t
WR
HIGH Z
CS
1-4
#
OE
#
I/O
7
ADDRESS
TOGGLE BIT: In addition to DATA# Polling another method for determining the end of
a write cycle is provided. During the write operation, successive attempts to read data
from the device will result in I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may
begin at any time during the write cycle.
NOTE:
1. Toggling either OE# or CS# or both OE# and CS# will operate toggle bit.
2. Beginning and ending state of I/O6 will vary
3. Any address location may be used but the address should not vary.
TOGGLE BUT CHARACTERISTICS
(1)
Symbol
Parameter
Min
Max
Units
t
DH
Data Hold Time
10
ns
t
OEH
OE# Hold Time
10
ns
t
OE
OE# to Output Delay
ns
t
OEHP
OE# High Pulse
150
ns
tWR
Write Recovery Time
0
ns
t
WR
HIGH Z
t
DH
t
OE
t
OEH
WE#
CS#
OE#
I/O6
(2)
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PAGE WRITE OPERATION
The WE128K32-XXX has a page write operation that
allows one to 128 bytes of data to be written into the device
and consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the fi rst data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150s
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
The usual procedure is to increment the least signifi cant
address lines from A0 through A6 at each write cycle. In
this manner a page of up to 128 bytes can be loaded in
to the EEPROM in a burst mode before beginning the
relatively long interval programming cycle.
After the 150s time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
FIGURE 9 PAGE MODE WRITE WAVEFORMS
PAGE WRITE CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C)
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min
Max
Write Cycle Time, TYP = 6ms
t
WC
10
ms
Address Set-up Time
t
AS
0
ns
Address Hold Time (1)
t
AH
100
ns
Data Set-up Time
t
DS
50
ns
Data Hold Time
t
DH
10
ns
Write Pulse Width
t
WP
100
ns
Byte Load Cycle Time
t
BLC
150
s
Write Pulse Width High
t
WPH
50
ns
1. Page address must remain valid for duration of write cycle.
OE#
CS#
WE#
ADDRESS
DATA
9
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 10 SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM
(1)
NOTES:
1. Data Format: D7 - D0 (Hex);
Address
Format:
A
16
- A
0
(Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 128 bytes of data to be loaded.
WRITES ENABLED
(2)
ENTER DATA
PROTECT STATE
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE128K32-XXX. These are included to improve reliability
during normal operation:
a) V
CC
power on delay
As
V
CC
climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b) V
CC
sense
While below 3.8V typical write cycles are inhibited.
c) Write
inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d) Noise
fi lter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the WE-128K32-XXX has the feature
disabled. Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of t
WC
. The write protection feature can be disabled by
a six byte write sequence of specifi c data to specifi c
locations. Power transitions will not reset the software
write protection.
Each 128K byte block of the EEPROM has independent
write protection. One or more blocks may be enabled and
the rest disabled in any combination. The software write
protection guards against inadvertent writes during power
transitions, or unauthorized modifi cation using a PROM
programmer.
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if
no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS
FIGURE 10
SOFTWARE BLOCK DATA PROTECTION
DISABLE ALGORITHM
(1)
EXIT DATA
PROTECT STATE
(3)
11
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
4.60 (0.181)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
12
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
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White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
NC
I/O
0
I/O
1
I/O
2
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
#
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
NC
A
13
A
8
I/O
16
I/O
17
I/O
18
V
CC
CS
4
#
WE
4
#
I/O
27
A
4
A
5
A
5
WE
3
#
CS
3
#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q
=
Compliant
M = Military Screened
-55C to +125C
I = Industrial
-40C to +85C
C
=
Commercial
0C
to
+70C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400*)
G2T = 22.4mm Ceramic Quad Flat Pack, Low Profi le CQFP (Package 509)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
P = Alternate Pin Confi guration for HIP package
ORGANIZATION 128K x 32
User Confi gurable as 256K x 16 or 512K x 8
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
ORDERING INFORMATION
W E 128K32 X - XXX X X X
Pin Description
I/O0-31
Data Inputs/Outputs
A0-16
Address Inputs
WE1-4#
Write Enables
CS1-4#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC Not
Connected
FIGURE 12 ALTERNATE PIN CONFIGURATION FOR WE128K32NP-XH1X
Block Diagram
128K x 8
8
I / O
0 - 7
W E
1
# CS
1
#
W E
2
# CS
2
#
W E
3
# CS
3
#
W E
4
# CS
4
#
128K x 8
8
I / O
8 - 1 5
128K x 8
8
I / O
1 6 - 2 3
128K x 8
8
I / O
2 4 - 3 1
A
0 - 1 6
O E #
Top View
14
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE128K32-XXX
March 2006
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 32 EEPROM Module
300ns
66 pin HIP (H1)
5962-94585 01H5X
128K x 32 EEPROM Module
250ns
66 pin HIP (H1)
5962-94585 02H5X
128K x 32 EEPROM Module
200ns
66 pin HIP (H1)
5962-94585 03H5X
128K x 32 EEPROM Module
150ns
66 pin HIP (H1)
5962-94585 04H5X
128K x 32 EEPROM Module
140ns
66 pin HIP (H1)
5962-94585 05H5X
128K x 32 EEPROM Module
300ns
66 pin HIP (H1, P type pinout)
5962-94585 01H6X
128K x 32 EEPROM Module
250ns
66 pin HIP (H1, P type pinout)
5962-94585 02H6X
128K x 32 EEPROM Module
200ns
66 pin HIP (H1, P type pinout)
5962-94585 03H6X
128K x 32 EEPROM Module
150ns
66 pin HIP (H1, P type pinout)
5962-94585 04H6X
128K x 32 EEPROM Module
140ns
66 pin HIP (H1, P type pinout)
5962-94585 05H6X
128K x 32 EEPROM Module
300ns
68 lead CQFP/J (G2T)
5962-94585 01HMX
128K x 32 EEPROM Module
250ns
68 lead CQFP/J (G2T)
5962-94585 02HMX
128K x 32 EEPROM Module
200ns
68 lead CQFP/J (G2T)
5962-94585 03HMX
128K x 32 EEPROM Module
150ns
68 lead CQFP/J (G2T)
5962-94585 04HMX
128K x 32 EEPROM Module
140ns
68 lead CQFP/J (G2T)
5962-94585 05HMX
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