1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE128K32-XXX
White Electronic Designs
128Kx32 EEPROM MODULE, SMD 5962-94585
TOP VIEW
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-16
Address Inputs
WE
1-4
Write Enables
CS
1-4
Chip Selects
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
B
LOCK
D
IAGRAM
FEATURES
Access Times of 120*, 140, 150, 200, 250, 300ns
Packaging:
66-pin, PGA Type, 27.3mm (1.075") square,
Hermetic Ceramic HIP (Package 400)
68 lead, 22.4mm sq. CQFP (G2U), 4.57mm
(0.180") high, (Package 509)
68 lead, 23.9mm sq. Low Profile CQFP (G1U)
1
,
3.57mm (0.140") high, (Package 519)
68 lead, 23.9mm sq. Low Profile CQFP (G1T),
4.06mm (0.160") high, (Package 524)
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Write Endurance 10,000 Cycles
Data Retention Ten Years Minimum (at +25C)
Commercial, Industrial and Military Temperature
Ranges
Low Power CMOS
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5 Volt Power Supply
Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation
Weight
WE128K32-XG2UX - 8 grams typical
WE128K32-XG1UX - 5 grams typical
WE128K32-XG1TX
1
- 5 grams typical
WE128K32-XH1X - 13 grams typical
*
120ns not available for SMD product
Note 1: Package Not Recommended For New Design
F
IG
. 1 P
IN
C
ONFIGURATION
FOR
WE128K32N-XH1X
May 2003 Rev. 7
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE128K32-XXX
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
T
RUTH
T
ABLE
AC T
EST
C
ONDITIONS
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH
are adjusted to simulate a typical resistive load
circuit.
ATE tester includes jig capacitance.
R
ECOMMENDED
O
PERATING
C
ONDITIONS
DC C
HARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C)
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Parameter
Symbol
Unit
Operating Temperature
T
A
-55 to +125
C
Storage Temperature
T
STG
-65 to +150
C
Signal Voltage Relative to GND
V
G
-0.6 to +6.25
V
Voltage on OE and A9
-0.6 to +13.5
V
NOTE:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect
device reliability.
CS
OE
WE
Mode
Data I/O
H
X
X
Standby
High Z
L
L
H
Read
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
High Z/Data Out
X
X
H
Write
X
L
X
Inhibit
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.0
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.5
+0.8
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Operating Temp. (Ind.)
T
A
-40
+85
C
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LOx32
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current x 32 Mode
I
CCx32
CS = V
IL
, OE = V
IH
, f = 5MHz
250
mA
Standby Current
I
SB
CS = V
IH
, OE = V
IH
, f = 5MHz
2.5
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA, V
CC
= 4.5V
0.45
V
Output High Voltage
V
OH
I
OH
= -400A, V
CC
= 4.5V
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
C
APACITANCE
(T
A
= +25C)
Parameter
Symbol
Conditions
Max Unit
OE capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
50
pF
WE
1-4
capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
pF
HIP (PGA)
20
CQFP G2U/G1U/G1T
20
CS
1-4
capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
20
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
20
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
50
pF
This parameter is guaranteed by design but not tested.
F
IG
. 4 AC T
EST
C
IRCUIT
NOTES:
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WE128K32-XXX
White Electronic Designs
WRITE
A write cycle is initiated when OE is high and a low
pulse is on WE or CS with CS or WE low. The
address is latched on the falling edge of CS or WE
whichever occurs last. The data is latched by the
rising edge of CS or WE, whichever occurs first. A
byte write operation will automatically continue to
completion.
WRITE CYCLE TIMING
Figures 5 and 6 show the write cycle timing relation-
ships. A write cycle begins with address application,
write enable and chip select. Chip select is accom-
plished by placing the CS line low. Write enable
consists of setting the WE line low. The write cycle
begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates
an internal 150 sec delay timer to permit page mode
operation. Each subsequent WE transition from high
to low that occurs before the completion of the 150
sec time out will restart the timer from zero. The
operation of the timer is the same as a retriggerable
one-shot.
AC WRITE CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C
TO
+125C)
Write Cycle Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
t
WC
10
ms
Address Set-up Time
t
AS
0
ns
Write Pulse Width (WE or CS)
t
WP
150
ns
Chip Select Set-up Time
t
CS
0
ns
Address Hold Time
t
AH
100
ns
Data Hold Time
t
DH
10
ns
Chip Select Hold Time
t
CSH
0
ns
Data Set-up Time
t
DS
100
ns
Output Enable Set-up Time
t
OES
10
ns
Output Enable Hold Time
t
OEH
10
ns
Write Pulse Width High
t
WPH
50
ns
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