1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
Access Times of 80**, 90, 120, 150ns
MIL-STD-883 Compliant Devices Available
Packaging:
68 lead, Hermetic CQFP (G2U), 122.4mm
(0.880") square, 3.56mm (0.140") height
(Package 510).
66-pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400)
* This product is subject to change without notice.
** 80ns speed is not fully characterized and is subject to change or cancellation without
notice.
Data Retention at 25C, 10 Years
Write Endurance, 10,000 Cycles
Organized as 32Kx32; User Confi gurable 64Kx16
or 128Kx8
Commercial, Industrial and Military Temperature
Ranges
Automatic
Page
Write
Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5
Volt
Power
Supply
Low Power CMOS, 10mA Standby Typical
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Top View
Block Diagram
32K x 8
8
I / O
0 - 7
W E
1
# CS
1
#
W E
2
# CS
2
#
W E
3
# CS
3
#
W E
4
# CS
4
32K x 8
8
I / O
8 - 1 5
32K x 8
8
I / O
1 6 - 2 3
32K x 8
8
I / O
2 4 - 3 1
A
0 - 1 4
O E #
I/O
8
I/O
9
I/O
10
A
13
A
14
NC
NC
NC
I/O
0
I/O
1
I/O
2
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
FIGURE 1 PIN CONFIGURATION FOR
WE32K32N-XH1X
Pin Description
I/O0-31
Data Input/Output
A0-14
Address Inputs
WE1-4#
Write Enable
CS1-4#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 2 PIN CONFIGURATION FOR WE32K32-XG2UX
Block Diagram
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
NC
NC
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
32K x 8
8
I / O
0 - 7
W E
1
# CS
1
#
W E
2
# CS
2
#
W E
3
# CS
3
#
W E
4
# CS
4
#
32K x 8
8
I / O
8 - 1 5
32K x 8
8
I / O
1 6 - 2 3
32K x 8
8
I / O
2 4 - 3 1
A
0 - 1 4
O E #
Pin Description
I/O0-31
Data Input/Output
A0-14
Address Inputs
WE1-4#
Write Enable
CS1-4#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 3
AC Test Circuit
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Parameter
Symbol
Conditions
-80
-90
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
10
10
10
A
Output Leakage Current
I
LOx32
CS# = V
IH
, OE# = V
IH
, V
OU
T = GND to
V
CC
10
10
10
10
A
Operating Supply Current (x32)
I
CCx32
CS# = V
IL
, OE# = V
IH
, f = 5MHz
320
250
200
150
mA
Standby Current
I
SB
CS# = V
IH
, OE# = V
IH
, f = 5MHz
2.5
2.5
2.5
2.5
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA, V
CC
= 4.5V
0.45
0.45
0.45
0.45
V
Output High Voltage
V
OH
I
OH
= -400A, V
CC
= 4.5V
2.4
2.4
2.4
2.4
V
TRUTH TABLE
CS#
OE#
WE#
Mode
Data I/O
H
X
X
Standby
High Z
L
L
H
Read
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
High Z/Data Out
X
X
H
Write
X
L
X
Inhibit
CAPACITANCE
T
A
= +25C
Parameter
Symbol
Conditions Max Unit
Address input capacitance
OE# capacitance
C
AD
C
OE
VIN = 0 V, f = 1.0 MHz
50
pF
WE# capacitance
C
WE
VIN = 0 V, f = 1.0 MHz
50
pF
CS1-4# capacitance
C
CS
VIN = 0 V, f = 1.0 MHz
25
pF
Data I/O capacitance
C
I/O
VI/O = 0 V, f = 1.0 MHz
40
pF
This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Operating Temperature
T
A
-55 to +125
C
Storage Temperature
T
S
T
G
-65 to +150
C
Signal Voltage Relative to GND
V
G
-0.6 to + 6.25
V
Voltage on OE# and A9
-0.6 to +13.5
V
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specifi cation is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.0
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.3
+0.8
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Operating Temp. (Ind.)
T
A
-40
+85
C
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC Write Characteristics
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
WRITE CYCLE
Write Cycle Parameter
Symbol
-80
-90
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
t
WC
10
10
10
10
ms
Address Set-up Time
t
AS
0
0
30
30
ns
Write Pulse Width (WE# or CS#)
t
WP
100
100
150
150
ns
Chip Select Set-up Time
t
CS
0
0
0
0
ns
Address Hold Time
t
AH
50
50
100
100
ns
Data Hold Time
t
DH
0
0
10
10
ns
Chip Select Hold Time
t
CSH
0
0
0
0
ns
Data Set-up Time
t
DS
50
50
100
100
ns
Write Pulse Width High
t
WPH
50
50
50
50
ns
Output Enable Set-up Time
t
OES
10
10
10
10
ns
Output Enable Hold Time
t
OEH
10
10
10
10
ns
WRITE
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs fi rst. A byte write operation will
automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150 sec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 sec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 4 WRITE WAVEFORMS WE# CONTROLLED
FIGURE 5 WRITE WAVEFORMS CS# CONTROLLED
t
ADDRESS
CS
1-4
#
WE
1-4
#
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE#
t
WC
t
DS
t
ADDRESS
WE
1 - 4#
CS
1 - 4#
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE#
t
DS
t
WC
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