1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED2DL32512V
January 2002 Rev. 2
ECO# 14663
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC's 16Mb SyncBurst SRAMs
integrate two 512K x 16 SRAMs into a single BGA package
to provide 512K x 32 configuration. All synchronous in-
puts pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The synchronous inputs
include all addresses, all data inputs, active LOW chip en-
able (CE), burst control input (ADSC) and byte write en-
ables (BW
0-3
). Asynchronous inputs include the output
enable (OE), clock (CLK) and snooze enable (ZZ). There
is also a burst mode input (MODE) that selects between
interleaved and linear burst modes. Write cycles can be
from one to four bytes wide, as controlled by the write
control inputs. Burst operation can be initiated with the
address status controller (ADSC) input.
512Kx32 Synchronous Pipeline Burst SR
512Kx32 Synchronous Pipeline Burst SR
512Kx32 Synchronous Pipeline Burst SR
512Kx32 Synchronous Pipeline Burst SR
512Kx32 Synchronous Pipeline Burst SRAM
AM
AM
AM
AM
FEATURES
n
Fast clock speed: 200, 166, 150 & 133MHz
n
Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
n
Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
n
Single +3.3V power supply (V
DD
)
n
Separate +3.3V or +2.5V isolated output buffer
supply (V
DDQ
)
n
Snooze Mode for reduced-power standby
n
Single-cycle deselect
n
Common data inputs and data outputs
n
Individual Byte Write control and Global Write
n
Clock-controlled and registered addresses, data I/Os
and control signals
n
Burst control (interleaved or linear burst)
n
Packaging:
119-bump BGA package
n
Low capacitive bus loading
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
SA
SA
ADSC
SA
SA
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ
C
NC
V
SS
NC
V
SS
NC
DQ
B
E
DQ
C
DQ
C
V
SS
CE
V
SS
DQ
B
DQ
B
F
V
DDQ
DQ
C
Vss
OE
V
SS
DQ
B
V
DDQ
G
DQ
C
DQ
C
BW
C
NC
BW
B
DQ
B
DQ
B
H
DQ
C
DQ
C
V
SS
NC
V
SS
DQ
B
DQ
B
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ
D
DQ
D
V
SS
CLK
V
SS
DQ
A
DQ
A
L
DQ
D
DQ
D
BW
D
NC
BW
A
DQ
A
DQ
A
M
V
DDQ
DQ
D
V
SS
BWE
V
SS
DQ
A
V
DDQ
N
DQ
D
DQ
D
V
SS
SA
1
V
SS
DQ
A
DQ
A
P
DQ
D
NC
V
SS
SA
0
V
SS
NC
DQ
A
R
NC
SA
MODE
V
DD
NC
SA
NC
T
NC
NC
SA
SA
SA
NC
ZZ
U
V
DDQ
DC
DC
DC
DC
NC
V
DDQ
DQ
B
DQ
A
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BW
A
BW
B
512K x 16
SSRAM
DQ
D
DQ
C
512K x 16
SSRAM
BW
C
BW
D
NOTE: DC = Do Not Connect
2
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WED2DL32512V
Symbol
Type
Description
CLK
Input
Pulse
The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
4P
SA
0
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising
4N
SA
1
edge of CLK.
2A, 2C, 2R, 2B
SA
3A, 3B, 3C, 3T
4T, 5A, 5B, 5C,
5T, 6A, 6B, 6C, 6R
5L
BW
A
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet
5G
BW
B
the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and
3G
BW
C
HIGH for a READ cycle.
3L
BW
D
BW
A
controls DQ
A
's and DQP
A
; BW
B
controls DQ
B
's and DQP
B
; BW
C
controls DQ
C
's and DQP
C
; BW
D
controls
DQ
D
's and DQP
D
.
4M
BWE
Input
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold
times around the rising edge of CLK.
4K
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its
rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge.
4E
CE
Input
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use
of ADSP. CE is sampled only when a new external address is loaded.
7T
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode
in which all data in the memory array is retained. When active, all other inputs are ignored.
4F
OE
Input
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
4B
ADSC
Input
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new
external address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is
also used to place the chip into power-down state when CE is HIGH.
3R
MODE
Input
Mode: This input selects the burst sequence. A LOW on MODE selects "linear burst." NC or HIGH on this input
selects "interleaved burst." Do not alter input state while device is operating.
(a) 6K, 6L, 6M, 6N,
DQ
A
Input/
SRAM Data I/Os: Byte "
A
" is DQ
A
's; Byte "
B
" is DQ
B
's; Byte "
C
" is DQ
C
's;
7K, 7L, 7N, 7P
Output
Byte "
D
" is DQd's. Input data must meet setup and hold times around rising edge of CLK.
(b) 6E, 6F, 6G, 6H,
DQ
B
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H
DQ
C
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
DQ
D
2K, 2L, 2M, 2N
2J, 4C, 4J, 4R, 6J,
V
DD
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
1A, 1F, 1J, 1M 1U
V
DDQ
Supply
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating
7A, 7F, 7J, 7M, 7U
Conditions for range.
3D, 3E, 3F, 3H, 3K,
V
SS
Supply
Ground: GND.
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
PIN DESCRIPTION
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED2DL32512V
Function
Address
CE
ZZ
ADSC
WRITE
OE
CLK
DQ
Used
Deselected Cycle, Power-Down
None
H
L
L
X
X
L-H
High-Z
Deselected Cycle, Power-Down
None
L
L
L
X
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
H
X
X
X
X
High-Z
WRITE Cycle, Begin Burst
External
L
L
L
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
L
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
L
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
X
L
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
L
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
L
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
L
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
L
H
L
X
L-H
D
NOTES:
1. X means "Don't Care." -- means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE, L means any one or more byte write enable signals (BW
A
, BW
B
, BW
C
or BW
D
) and BWE are LOW.
3. BW
A
enables WRITEs to DQ
A
's and DQP
A
. BW
B
enables WRITEs to DQ
B
's. BW
C
enables WRITEs to DQ
C
's. BW
D
enables WRITEs to DQ
D
's.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
INTERLEAVED BURST TABLE
(MODE = NC OR HIGH)
First Address Second Address
Third Address
Fourth Address
External
Internal
Internal
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
INTERLEAVED BURST TABLE
(MODE = LOW)
First Address Second Address Third Address
Fourth Address
External
Internal
Internal
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
TRUTH TABLE
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WED2DL32512V
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
Voltage on V
DD
Supply relative to V
SS
-0.5V to +4.6V
Voltage on V
DDQ
Supply relative to V
SS
-0.5V to +4.6V
V
IN
(DQ
X
)
-0.5V to V
DDQ
+0.5V
V
IN
(Inputs)
-0.5V to V
DD
+0.5V
Storage Temperature (BGA)
-55C to +125C
Short Circuit Output Current
100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ELECTRICAL C
HARACTERISTICS
Description
Symbol
Conditions
Min
Max
Units
Notes
Input High (Logic 1)Voltage
V
IH
2.0
V
DD
+0.3
V
1
Input Low (Logic 0) Voltage
V
IL
-0.3
0.8
V
1
Input Leakage Current
I
LI
0V
V
IN
V
DD
-1.0
1.0
A
2
Ouptut Leakage Current
I
LO
Output(s) disabled, 0V
V
IN
V
DD
-1.0
1.0
A
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
--
V
1
Output Low Voltage
V
OL
I
OL
= 8.0mA
--
0.4
V
1
Supply Voltage
V
DD
3.135
3.6
V
1
Isolated Output Buffer Supply
V
DDQ
3.134
3.6
V
Description
Conditions
Symbol
Typ
Max
Units
Notes
Control Input Capacitance
T
A
= 25C; f = 1MHz
C
I
3
6
pF
1
Input/Output Capacitance (DQ)
T
A
= 25C; f = 1MHz
C
O
4
5
pF
1
Address Capacitance
T
A
= 25C; f = 1MHz
C
A
3
5
pF
1
Clock Capacitance
T
A
= 25C; f = 1MHz
C
CK
2.5
4
pF
1
NOTES:
1. This parameter is sampled.
BGA CAPACITANCE
PARTIAL TRUTH TABLE - WRITE COMMANDS
Function
BWE
BW
A
BW
B
BW
C
BW
D
Read
H
X
X
X
X
Read
L
H
H
H
H
Write Byte "
A
"
L
L
H
H
H
Write All Bytes
L
L
L
L
L
Note:
Using BWE and BW
A
through BW
D
, any one or more bytes may be written.
Description
Symbol
Conditions
Typ
200
166
150
133 Units Notes
MHz
MHz
MHz
MHz
Power Supply
Device selected; All inputs
V
IL
or 3 V
IH
; Cycle time 3 t
KC
MIN;
Current: Operating
I
DD
V
DD
= MAX; Outputs open
950
800
740
600
mA
1,2,3
Device deselected; V
DD
= MAX; All inputs
Vss + 0.2
CMOS Standby
I
SB
2
or V
DD
- 0.2; All inputs static; CLK frequency = 0
10
20
20
20
20
mA
2,3
Device deselected; V
DD
= MAX; All inputs
V
IL
or V
IH
;
TTL Standby
I
SB
3
All inputs static; CLD frequency = 0
20
40
40
40
40
mA
2,3
Device deselected; V
DD
= MAX; All inputs
VSS + 0.2
Clock Running
I
SB
4
or V
DD
-0.2; Cycle time 3 t
KC
MIN
80
220
180
160
140
mA
2,3
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
increases with faster cycle times and greater output loading.
2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down
mode).
3. Typical values are measured at 3.3V, 25C and 133MHz.
DC C
HARACTERISTICS
NOTES:
1. All voltages referenced to Vss (GND).
2. MODE has an internal pull-up, and input leakage = 10A.
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED2DL32512V
AC C
HARACTERISTICS
Symbol
200MHz
166MHz
150MHz
133MHz
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock
Clock Cycle Time
t
KC
5.0
6.0
6.6
7.5
ns
Clock Frequency
t
KF
200
166
150
133
MHz
Clock HIGH Time
t
KH
2.0
2.4
2.6
2.6
ns
Clock LOW Time
t
KL
2.0
2.4
2.6
2.6
ns
Output Times
Clock to output valid
t
KQ
2.5
3.5
3.8
4.0
ns
Clock to output invalid
2
t
KQX
1.5
1.25
1.25
1.5
ns
Clock to output on Low-Z
2,3,4
t
KQLZ
0
0
0
0
ns
Clock to output in High-Z
2,3,4
t
KQHZ
3.0
3.5
3.8
4.0
ns
OE to output valid
5
t
OEQ
2.5
3.5
3.8
4.0
ns
OE to output in Low-Z
2,3,4
t
OELZ
0
0
0
0
ns
OE to output in High Z
2,3,4
t
OEHZ
2.5
3.5
3.8
4.0
ns
Setup Times
Address
6,7
t
AS
1.5
1.5
1.5
1.5
ns
Address status (ADSC)
6,7
t
ADSS
1.5
1.5
1.5
1.5
ns
Write signals (BW
A
-BW
D
, BWE)
6,7
t
WS
1.5
1.5
1.5
1.5
ns
Data-in
6,7
t
DS
1.5
1.5
1.5
1.5
ns
Chip enables (CE)
6,7
t
CES
1.5
1.5
1.5
1.5
ns
Hold Times
Address
6,7
t
AH
0.5
0.5
0.5
0.5
ns
Address status (ADSC)
6,7
t
ADSH
0.5
0.5
0.5
0.5
ns
Write Signals (BW
A
-BW
D
, BWE)
6,7
t
WH
0.5
0.5
0.5
0.5
ns
Data-in
6,7
t
DH
0.5
0.5
0.5
0.5
ns
Chip Enables (CE)
6,7
t
CEH
0.5
0.5
0.5
0.5
ns
NOTES:
1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted.
2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0.
3. This parameter is sampled.
4. Transition is measured 500mV from steady state voltage.
5. OE is a "Don't Care" when a byte write enable is sampled LOW.
6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables
HIGH and ADSC LOW for the required setup and hold times.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled.
All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled.
Chip enable must be valid at each rising edge of CLK when ADSC is LOW to remain enabled.
OUTPUT LOADS
AC T
EST
C
ONDITIONS
Parameter
3.3V I/O
2.5V I/O
Unit
Input Pulse Levels
V
SS
to 3.0
V
SS
to 2.5
V
Input Rise and Fall Times
1
1
ns
Input Timing Reference Levels
1.5
1.25
V
Output Timing Reference Levels
1.5
1.25
V
Output Load
See figure, at left
AC Output Load Equivalent
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WED2DL32512V
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode In
which the device is deselected and current is reduced to
I
SB
2
Z
. The duration of SNOOZE MODE is dictated by the
length of time ZZ is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated in-
puts and are ignored. ZZ is an asynchronous, active HIGH
input that causes the device to enter SNOOZE MODE.
Description
Conditions
Symbol
Min
Max
Units
Notes
Current during SNOOZE MODE
ZZ
VIH
I
SB
2
Z
10
mA
ZZ active to input ignored
t
ZZ
2(t
KC
)
ns
1
ZZ inactive to input sampled
t
RZZ
2(t
KC
)
ns
1
ZZ active to snooze current
t
ZZI
2(t
KC
)
ns
1
ZZ inactive to exit snooze current
t
RZZI
ns
1
SNOOZE MODE
When ZZ becomes a logic HIGH, I
SB
2
Z
is guaranteed after
the setup time t
ZZ
is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.
FIG. 2 SNOOZE MODE TIMING DIAGRAM
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED2DL32512V
FIG. 3 READ TIMING DIAGRAM
NOTES:
1. Q (A
2
) refers to output from address A
2
. Q (A
2+1
) refers to output from the next internal burst address following A
2
.
8
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WED2DL32512V
FIG. 4 WRITE TIMING DIAGRAM
NOTES:
1. D (A
2
) refers to output from address A
2
. D (A
2+1
) refers to output from the next internal burst address following A
2
.
2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the
time period prior to the byte write enable inputs being sampled.
3. Full-width WRITE can be initiated by BWE, BW
A
, - BW
D
LOW. Timing is shown assuming that the device was not enabled before entering into its
sequence. OE does not cause Q to be driven until after the following clock rising edge.
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WED2DL32512V
ORDERING INFORMATION
512Kx32
Part Number
Config.
t
KQ
Clock Package
(ns) (MHz)
No.
Commercial Temp Range (0C to 70C)
WED2DL32512V25BC
512Kx32
2.5
200
435
WED2DL32512V35BC
512Kx32
3.5
166
435
WED2DL32512V38BC
512Kx32
3.8
150
435
WED2DL32512V40BC
512Kx32
4.0
133
435
Industrial Temp Range (-40C to +85C)*
WED2DL32512V38BI
512Kx32
3.8
150
435
WED2DL32512V40BI
512Kx32
4.0
133
435
* Advanced Information
PACKAGE DIMENSION: 119 BUMP PBGA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note:
Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined.
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